Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.

Abstract: A semiconductor package including: a first substrate including a first surface including a first region and a second region at least partially surrounding the first region, wherein the first substrate includes a first insulating layer, a first conductive pattern in the first insulating layer, a first passivation layer disposed in the first region and the second region, and a second passivation layer disposed on the first passivation layer in the second region; an interposer overlapping the first substrate and including a second insulating layer and a second conductive pattern in the second insulating layer; a first connection terminal disposed on the first passivation layer in the first region; and a second connection terminal disposed on the second passivation layer in the second region, wherein the first conductive pattern and the second conductive pattern are connected to each other through the first connection terminal and the second connection terminal.

Abstract: Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.

Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.

Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: Disclosed are a polyolefin resin composition and a production method using same. The polyolefin resin satisfies the following conditions: (1) melt index (MI2.16, 190° C., under a load of 2.16 kg) is 0.1 to 1.5 g/10 min; (2) density is 0.91 to 0.93 g/cc; (3) polydispersity Index (Mw (weight-average molecular weight)/Mn (number-average molecular weight)) is 3 to 7; (4) Mz (Z-average molecular weight)/Mw (weight-average molecular weight) is 2.3 to 4.5; and (5) COI(Comonomer Orthogonal Index) value calculated by Equation 1 in the specification is 5 to 12. In Equation 1, “SCB number at Mz” represents average number of branches derived from comonomers per 1000 carbon atoms at Z-average molecular weight (Mz), and “SCB number at Mn” represents average number of branches derived from comonomers per 1000 carbon atoms at number-average molecular weight (Mn) based on a molecular weight-comonomer distribution graph.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.

Abstract: Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A separate reference voltage for each data receiver compensates for variations between data paths, and provides for a wider data valid window than if the same reference voltage were used for all data receivers. Generating the different reference voltages on-die can potentially require a large area, as well as consume considerable power and/or current. A voltage divider and multiplexers may provide the different reference voltages, which saves space and is power and current efficient.

Abstract: A bidirectional flow-controllable artificial respirator, according to one embodiment, comprises: a chamber for storing air; a tube connected to the chamber and having air flowing therein; a mask connected to the tube and mounted on a face or mouth; and a flow control valve unit provided in the tube and controlling the air flow between the chamber or an air supply source, and the mask. The flow control valve unit comprises: a first valve allowing an air supply path from the air supply source toward the mask; and a second valve allowing an air discharge path from the mask toward the outside of the respirator, wherein the first valve and the second valve are alternately opened and closed during artificial respiration, the first valve is blocked during chest compressions so that negative pressure in a subject receiving air is maintained for a long period, and the first valve and the second valve may be selectively opened and closed so as to allow air to be supplied according to a preset air supplying period.

Abstract: A method of estimating a state of health of a battery, the method being performed by a computing apparatus, the method including: preparing a trained artificial neural network; generating input data by measuring at least one parameter of a battery; acquiring a plurality of output values each corresponding to a plurality of classes by inputting the input data into the trained artificial neural network; and generating a state of health estimation value of the battery using a plurality of preset health state sections each corresponding to the plurality of classes and the plurality of output values each corresponding to the plurality of classes.

Abstract: Disclosed is an antistatic agent for a metallocene olefin polymerization process and a polymerization method using the same, by which discontinuity event due to sheeting or drooling occurring in the olefin polymerization process can be effectively reduced, enabling continuous operation for a long time, and the obtained final product can be applied to various applications including food contact use. The present disclosure includes an olefin polymerization method, which comprises forming a mixture in which an antistatic agent containing diglycerol oleate is mixed with a low molecular weight hydrocarbon, supplying the antistatic agent mixture and a metallocene-based catalyst composition comprising a metallocene catalyst and aluminoxane to two or more polymerization reactors, and polymerizing one or more alpha-olefins in the presence of the antistatic agent mixture and catalyst composition.

Abstract: A catalyst composition for polymerizing a polyolefin having excellent processability and impact strength, a process for producing a polyolefin and a polyolefin resin thereof are disclosed. The catalyst composition comprises at least one first organometallic compound of following formula 1; at least one second organometallic compound of following formula 2; and aluminoxane. The polyolefin resin satisfies following properties (i) to (iv) and (vi), (i) melt flow index (ASTM D1238), measured at 190° C., under a load of 2.16 kg: 0.1 to 1.5 g/10 min, (ii) density: 910 to 930 kg/m3, (iii) the ratio (Mw/Mn), as measured by gel permeation chromatography (GPC): 3.0 to 7.0, (iv) the ratio (Mz/Mw), as measured by GPC: 2.2 to 4.5, and (vi) when the TREF curve of multimodal distribution is deconvoluted, the area of TREF curve having a peak at 50 to 74° C. is 40 to 75% of the total area of the TREF curve.

Abstract: A semiconductor package including: a first substrate including a first surface including a first region and a second region at least partially surrounding the first region, wherein the first substrate includes a first insulating layer, a first conductive pattern in the first insulating layer, a first passivation layer disposed in the first region and the second region, and a second passivation layer disposed on the first passivation layer in the second region; an interposer overlapping the first substrate and including a second insulating layer and a second conductive pattern in the second insulating layer; a first connection terminal disposed on the first passivation layer in the first region; and a second connection terminal disposed on the second passivation layer in the second region, wherein the first conductive pattern and the second conductive pattern are connected to each other through the first connection terminal and the second connection terminal.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.