Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

Abstract: A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

Abstract: A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.

Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.

Abstract: Computer systems may include multiple power switch circuits for coupling circuit blocks to power supply signals. Different power supply signals may be selected for use in the generation a control signal for a power switch device in the power switch circuit. For example, during a particular operating mode of a power switch circuit coupled to a circuit block, a power supply signal with a voltage level greater than an power supply signal for the circuit block may be used to generate the control signal.

Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

Abstract: Computer systems may include multiple power switch circuits for coupling circuit blocks to power supply signals. Different power supply signals may be selected for use in the generation a control signal for a power switch device in the power switch circuit. For example, during a particular operating mode of a power switch circuit coupled to a circuit block, a power supply signal with a voltage level greater than an power supply signal for the circuit block may be used to generate the control signal.

Abstract: Systems, apparatuses, and methods for reducing leakage current for a memory array. In various embodiments, techniques are implemented for generating a supply voltage for a memory array which tracks the data retention voltage of the memory array. In one embodiment, multiple diodes are implemented in parallel between a supply voltage and the memory array. The diodes have different sizes and different voltage drops, and the diode which will cause the voltage to drop closest to without going below the data retention voltage is selected for routing the supply voltage to the memory array. Since the data retention voltage for the memory array varies over temperature, the temperature of the system is monitored. Based on changes in the temperature, the system changes which diode is in the circuit path for supplying power to the memory array so as to reduce leakage current for the memory array.

Abstract: In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage.

Abstract: Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circuitry reduces a voltage potential across critical nodes of the sense amplifier circuit to a difference between a store voltage and Vdd when the store voltage is about to be applied to any of the one or more memory cells. The store protection circuitry connects Vdd to one or more of the critical nodes of the sense amplifier circuit when the store voltage is about to be applied to any of the one or more memory cells.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circuitry reduces a voltage potential across critical nodes of the sense amplifier circuit to a difference between a store voltage and Vdd when the store voltage is about to be applied to any of the one or more memory cells. The store protection circuitry connects Vdd to one or more of the critical nodes of the sense amplifier circuit when the store voltage is about to be applied to any of the one or more memory cells.

Abstract: Various apparatuses and methods in which a dual-polarity non-volatile memory cell includes a sense mode component and a charge mode component. The sense mode component communicates information stored in the dual-polarity non-volatile memory cell during a read operation. The charge mode component facilitates storing of the information stored in the dual-polarity non-volatile memory cell. The charge mode component includes a first coupling capacitor and a second tunneling capacitor in a first well, and a first tunneling capacitor and a second coupling capacitor in a second well.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.

Abstract: Various apparatuses and methods are shown in which an integrated circuit includes a dual-polarity non-volatile memory cell and a test circuit. The test circuit has a bias voltage generator and a first switch. The bias voltage generator couples to the dual-polarity non-volatile memory cell via the first switch.

Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

Abstract: Various apparatuses and methods in which an integrated circuit includes a non-volatile memory cell and a keep mode circuit. The non-volatile memory cell has a charge storage component. The keep mode circuit has a storage device and a keep mode switch. The storage device receives information stored in the non-volatile memory cell. The keep mode switch connects the storage device to the non-volatile memory cell in order to apply a static bias voltage across the charge storage component to restrict charge-loss to a predetermined level.

Abstract: A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.