Abstract: Self-referenced, built-in access shutdown mechanism for a memory circuit. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.

Abstract: Circuitry and method for effectuating low power read operations in a memory circuit, e.g., a memory instance having a banked architecture. When a memory read cycle is initiated with respect to a particular memory cell in a selected bank based on a plurality of address signals, a specific wordline associated with the memory cell is driven high. Upon waiting until the bitline coupled thereto reach a predetermined sense level, the wordline is shut off based on a reference memory cell structure, which wordline thereby stops driving the bitline. Subsequently, after waiting for a select time, the sense amplifier senses the data stored in the particular memory cell based a charge distribution between its internal node(s) and the bitline after the selected wordline is deactivated.

Abstract: A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier.

Abstract: A dual port memory device comprises a first group of bit lines corresponding to a first port of the device, a second group of bit lines corresponding to a second port of the device, and a vertical shielding layer disposed between the first group of bit lines and the second group of bit lines, for eliminating the capacitance coupling between the first group of bit lines and the second group of bit lines. The first group of bit lines are disposed in a first metal layer of the device, the vertical shielding is disposed in a second metal layer of the device, and the second group of bit lines are disposed in a third metal layer of the device. The present invention further comprises jumper lines for electrically connecting the bit lines in the metal layer above the vertical shielding layer to a diffusion well of a transistor. In addition, jumper windows are provided in the vertical shielding layer for allowing the jumper lines to pass through the vertical shielding layer.