Abstract: A three-dimensional ultrasonic mapping system may combine mechanical rotation with a multibeam ultrasonic transducer assembly using a combination of frequency and phase beamforming to steer linear arrays of transducer elements over a range of angles. An array may be divided into a number of channels that may be less than the number of transducer elements in the array. A phase difference between adjacent transducer elements may be an integer multiple of 360 degrees divided by the number of channels. The ultrasonic beamforming system of the transducer assembly may produce near real-time two-dimensional imaging. Mechanical rotation of the transducer assembly may enable three-dimensional ultrasonic mapping. In some implementations, an arrangement of multiple sets of two frequency and phase steered arrays may enable the three-dimensional ultrasonic mapping.

Abstract: A pill dispensing apparatus includes a carousel with at least one removable bin for storing pills, a vision system for identifying pills within the bin, a vacuum nozzle for removing one or more pills identified by the vision system, and a dispensing area for receipt of the removed pills.

Abstract: An exemplary voice monitoring system includes a wearable voice monitor and an auxiliary device such as a smart phone. The wearable monitor incorporates a wake-on-sound microphone, a vibration motor, and a microcontroller within a small, discreet enclosure. The enclosure can be hung from a necklace chain or affixed to clothing, like a piece of jewelry. The jewelry appearance is enhanced by a removable decorative piece. The microcontroller wakes up in response to a wake signal from the microphone when a voice sound of a wearer is detected. The microcontroller initiates measurements to determine if the voice sound meets preconfigured criteria and activates the vibration motor to alert the wearer. Sound criteria resulting in vibratory alerts are contained in a user-specific schedule tailored according to time of day and day of week. The smart phone can remotely create customized schedules and transmit them to the monitor.

Abstract: A pill dispensing apparatus includes a carousel with at least one removable bin for storing pills, a vision system for identifying pills within the bin, a vacuum nozzle for removing one or more pills identified by the vision system, and a dispensing area for receipt of the removed pills.

Abstract: A device including a ferroelectric memory and methods of manufacturing the same are provided. In one embodiment, the device includes a semiconductor die with an integrated circuit fabricated thereon, a stress buffer die mounted to the semiconductor die overlying the integrated circuit, and a molding compound encapsulating the semiconductor die and the stress buffer die. Generally the integrated circuit includes a ferroelectric memory. In some embodiments, the device further includes a polyimide layer between the stress buffer and the semiconductor die. Other embodiments are also provided.

Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract: Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column.

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Abstract: Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to the cells of the configuration data rows. This allows at least some of the circuitry utilized to access data from the primary array to be utilized to access the configuration data, which promotes an efficient use of resources among other things. Additionally, the configuration data can be transferred to volatile registers serially at startup to simplify routing and design and thereby conserve space. The volatile registers are operatively associated with configuration data circuitry that makes use of the configuration data at startup or later time(s).

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.