Patents by Inventor Jasmin Ajanovic

Jasmin Ajanovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884971
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: David Harriman, Jasmin Ajanovic
  • Patent number: 10685675
    Abstract: Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Inventor: Jasmin Ajanovic
  • Publication number: 20200110725
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Application
    Filed: July 22, 2019
    Publication date: April 9, 2020
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Jasmin Ajanovic
  • Patent number: 10360171
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: July 23, 2019
    Assignee: Intel Corporation
    Inventors: David Harriman, Jasmin Ajanovic
  • Publication number: 20180268855
    Abstract: Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Inventor: Jasmin Ajanovic
  • Patent number: 9990953
    Abstract: Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 5, 2018
    Inventor: Jasmin Ajanovic
  • Patent number: 9860173
    Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Patent number: 9836424
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9741384
    Abstract: Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 22, 2017
    Inventor: Jasmin Ajanovic
  • Patent number: 9736276
    Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Mahesh Wagh, Abhishek Singhal, Jasmin Ajanovic
  • Patent number: 9736071
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9602408
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9565106
    Abstract: A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee
  • Patent number: 9535838
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 9442855
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20160070671
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Application
    Filed: July 14, 2015
    Publication date: March 10, 2016
    Inventors: David Harriman, Jasmin Ajanovic
  • Patent number: 9098415
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 9088495
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Patent number: 9071528
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
  • Publication number: 20150178241
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 25, 2015
    Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee