Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet that includes a format field to partially specify the packet header format and a type field to specify a transaction type. The format field and the type field together specify the packet header format and the format field indicates the size of the packet header.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method according to one embodiment may include partitioning a multi-core processor into a first partition and a second partition, the first partition including a first processor core and a first interrupt controller configured to store a first partition identifier, the second partition including a second processor core and a second interrupt controller configured to store a second partition identifier. The method may also include receiving, by the first interrupt controller and the second interrupt controller, at least one interrupt that includes a partition identifier. The method may also include comparing, by the first interrupt controller, the partition identifier included with the interrupt to the first partition identifier stored in the first interrupt controller.

Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.

Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found then the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.

Abstract: A method and apparatus for implementing virtual wire signaling is described. It includes an apparatus including a first component, a bus coupled to the first component, the bus to transmit packets of data, and a second component coupled to the bus, messages passed between the first component and the second component through packets transmitted on the bus.

Abstract: A point-to-point interconnection and communication architecture, protocol and related methods. System resources are dynamically shared based on contents of information received for transmission within the system. Virtual channels may be used for transmission of the information received for transmission over a general input/output (GIO) bus.

Abstract: To reduce prefetch overshoot when prefetching partial data sets along the path from input-output bus to system memory, a prefetch field is used to communicate the amount of data that a prefetching entity upstream may prefetch. Utilizing a prefetch field in such a manner reduces the fetching of unneeded data past the end of the requested data, resulting in overall increased system performance.