Patents by Inventor Jason A. Janesky
Jason A. Janesky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103100Abstract: Embodiments are disclosed for yoke structures for improved magnetometer performance. In an embodiment, a magnetometer comprises: a yoke structure comprising at least one hard magnetic layer and at least one soft magnetic layer arranged along a dimension of the yoke structure, where a first coercivity of the at least one hard magnetic layer is greater than a second coercivity of the at least one soft magnetic layer; and at least one magnetic sensing element located in proximity to the at least one soft magnetic layer. In another embodiment, a magnetometer comprises: a multilayer yoke structure comprising layers of non-magnetic material and magnetic material along a dimension of the yoke structure; and at least one magnetic sensing element located in proximity to the yoke structure.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Jason Janesky, Savas Gider
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Publication number: 20240107892Abstract: The enclosed embodiments are directed to a magnetoresistance (MR) sensor with a biased free layer for improved stability of magnetic performance. In an embodiment, an MR sensor comprises: a first antiferromagnetic (AF) pinning layer; a magnetic fixed layer disposed on the first AF layer; a tunnel barrier disposed on the magnetic fixed layer; a magnetic coupled free layer disposed on the tunnel barrier; a AF coupling layer disposed on the magnetic coupled free layer; a magnetic pinned layer disposed on the AF coupling layer; and a second AF pinning layer disposed on the magnetic pinned layer. In an embodiment, a method of unpinning a pinned free layer uses a current pulse through the MR sensor to self-heat above a blocking temperature of the AF pinning layer, and then reading the MR sensor after the current pulse is reduced or removed and the MR sensor cools back below the blocking temperature.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Jason Janesky, Jodi M. Iwata-Harms, Savas Gider
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Patent number: 11925122Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.Type: GrantFiled: September 8, 2021Date of Patent: March 5, 2024Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
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Publication number: 20240006011Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Jason JANESKY, Han Kyu LEE, Hamid ALMASI, Pedro SANCHEZ, Cristian P. MASGRAS, Iftekhar RAHMAN, Sumio IKEGAWA, Sanjeev AGGARWAL, Dimitri HOUSSAMEDDINE, Frederick Charles NEUMEYER
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Patent number: 11798646Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.Type: GrantFiled: October 27, 2021Date of Patent: October 24, 2023Assignee: Everspin Technologies, Inc.Inventors: Syed M. Alam, Jason Janesky, Han Kyu Lee, Hamid Almasi, Pedro Sanchez, Cristian P. Masgras, Iftekhar Rahman, Sumio Ikegawa, Sanjeev Aggarwal, Dimitri Houssameddine, Frederick Charles Neumeyer
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Patent number: 11744161Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.Type: GrantFiled: December 14, 2020Date of Patent: August 29, 2023Assignee: Everspin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Patent number: 11488647Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.Type: GrantFiled: June 27, 2019Date of Patent: November 1, 2022Assignee: Everspin Technologies, Inc.Inventors: Jijun Sun, Frederick Mancoff, Jason Janesky, Kevin Conley, Lu Hui, Sumio Ikegawa
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Publication number: 20220139488Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.Type: ApplicationFiled: October 27, 2021Publication date: May 5, 2022Applicant: Everspin Technologies, Inc.Inventors: Syed M. ALAM, Jason JANESKY, Han Kyu LEE, Hamid ALMASI, Pedro SANCHEZ, Cristian P. MASGRAS, Iftekhar RAHMAN, Sumio IKEGAWA, Sanjeev AGGARWAL, Dimitri HOUSSAMEDDINE, Frederick Charles NEUMEYER
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Publication number: 20210408371Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.Type: ApplicationFiled: September 8, 2021Publication date: December 30, 2021Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason JANESKY
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Publication number: 20210375342Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.Type: ApplicationFiled: June 27, 2019Publication date: December 2, 2021Applicant: Everspin Technologies, Inc.Inventors: Jijun SUN, Frederick MANCOFF, Jason JANESKY, Kevin CONLEY, Lu HUI, Sumio IKEGAWA
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Patent number: 11139429Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.Type: GrantFiled: February 19, 2020Date of Patent: October 5, 2021Assignee: Everspin Technologies, Inc.Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
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Patent number: 11088317Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.Type: GrantFiled: March 16, 2018Date of Patent: August 10, 2021Assignee: Everspin Technologies, Inc.Inventors: Wenchin Lin, Jason Janesky
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Publication number: 20210135096Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Applicant: Everspin Technologies, Inc.Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
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Patent number: 10923170Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.Type: GrantFiled: March 19, 2019Date of Patent: February 16, 2021Assignee: Everspin Technologies, Inc.Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
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Patent number: 10897008Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.Type: GrantFiled: June 2, 2020Date of Patent: January 19, 2021Assignee: Everspin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Publication number: 20200295255Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (1) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may he disposed on the first layer.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Applicant: Everspin Technologies, Inc.Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
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Patent number: 10707410Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.Type: GrantFiled: December 19, 2018Date of Patent: July 7, 2020Assignee: Everspin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Publication number: 20200185602Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason Janesky
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Patent number: 10608172Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.Type: GrantFiled: January 24, 2019Date of Patent: March 31, 2020Assignee: Everspin Technologies, Inc.Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
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Patent number: 10600460Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results.Type: GrantFiled: October 11, 2018Date of Patent: March 24, 2020Assignee: Everspin Technologies, Inc.Inventors: Sarin Deshpande, Sanjeev Aggarwal, Jason Janesky, Jon Slaughter, Phillip Lopresti