Abstract: Photovoltaic systems with managed output and methods for managing variability of output from photovoltaic systems are described. A system includes a plurality of photovoltaic modules configured to receive and convert solar energy. The system also includes a sensor configured to determine an orientation for each of the plurality of photovoltaic modules, the orientations based on a maximum output from the photovoltaic system. The system also includes an orientation system configured to alter the orientation of one or more of the plurality of photovoltaic modules to provide a reduced output from the photovoltaic system, the reduced output less than the maximum output.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: Cavity enhanced spectroscopy efficiently couples a broadband optical frequency comb to a high finesse optical cavity inside which a sample test gas is placed. The output of the optical cavity is a multiplicity of channels of data resulting from the differential absorption of light at various of the comb frequencies. The device can operate in a ringdown mode or a non-ringdown enhanced absorption spectroscopy mode. Careful measurement and control of cavity dispersion and comb spacing are part of the coupling process. Several dispersive detection methods adapted to detecting the multiplicity of channels are provided.

Abstract: A solar collector assembly may include a frame supporting a solar collector and a frame member defining a tilted pivot axis. Support struts may be used to elevate one end of the frame and may be pivoted between an orientation generally parallel to the frame member and to an orientation generally away from the frame. Anchorless, ballast type bases may be used to support the solar collector assembly. Several assemblies may be stacked on top of one another in a storage or transportation configuration using spacers extending between the frames.

Abstract: An abrasive tool comprising of a base portion (2), having a foam layer (3) affixed to the abrasive tool base portion, and a plastic film layer (4) affixed, bonded or glued to the foam layer. This tool is adapted to receive an abrasive material layer (5) or sand paper or other abrasive material having a pressure sensitive adhesive applied to one side of the abrasive material, to allow said abrasive material to be stuck and affixed to the abrasive tool. The abrasive tool may be hand operated, or operated by electric power, air power, or other motive power.

Abstract: A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.

Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

Abstract: In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

Abstract: As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized processing without responding to signal transfer requests. Not only does the direct memory access controller control the exchange of signal groups between the memory unit and the core processing unit, but the direct memory access controller is also responsible for the transfer of signal groups within the digital signal processor that originate from the serial port, and the interface unit (the unit that implements the direct transfer of signal groups from the memory unit of one digital signal processor to a second signal processor). The direct memory access controller has programmable channels that permit the signal group source component to be coupled to the signal group destination component. The address unit of the direct memory access unit must be able to accommodate a plurality of addressing modes.

Abstract: A bi-directional pulsed ring laser that produces bi-directional light pulses that interact in such a way that they are phase conjugated. A nonlinear substance, such as a nonlinear crystal or fluid, that has an index of refraction that is dependent upon light intensity is located near a beam waist of the laser cavity to provide a self-lensing effect. Methods for reducing dead band beyond observable limits are also provided. The increased sensitivity of the bi-directional pulsed ring laser provides application in detecting magnetic susceptibility by detecting the change in phase between the arrival times of the bi-directional pulses at a modulator and the electrical signal of the modulator to determine the change in frequency of a coil that has magnetic susceptibility.

Abstract: A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect data from single channels or from multiple channels and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays. The coalescing prestage may include one or more first registers, a delay register, multiplexers to select outputs of the first registers, and multiplexers to select outputs of the delay register. Alternatively, the coalescing prestage may include one or more register array structures, each such structure having independent write ports, one for each channel. Data coalesced in the coalescing prestage is provided to a primary stage. The primary stage may include one or more logical register arrays configured as one physical array.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Abstract: A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.