Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits.

Abstract: Embodiments include methods, design layout optimization systems, and computer program products for optimizing design layout of integrated circuits.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid, at least one inductor, at least one tunable resistance switch, and a capacitor network. The tunable sector buffer is programmable to set latency and slew rate of the clock signal. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Abstract: A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.