Abstract: An integrated mass spectrometer electrospray emitter and fluorescence detector allows improved volumetric measurements of separate components from a liquid chromatography column by improving correlation between the readings of these instruments and reducing dead volume and sample size requirements.

Abstract: A vision recognition system is provided for use with a high speed, automatic produce labeling machine. The system uses laser profiling to direct a sheet of light transversely to the longitudinal axis of a produce feed conveyor. The sheet of light periodically impacts, and generates laser profiles of, the surfaces of the produce items, such as pears, being fed by the conveyor to one or more labeling machines. The laser profiles are used to generate real world (x,y) coordinates of the domes of the incoming produce items, which are passed to the labeling machine or machines. Real world height (or z) coordinates may also be created and passed to the labeler.

Abstract: An integrated mass spectrometer electrospray emitter and fluorescence detector allows improved volumetric measurements of separate components from a liquid chromatography column by improving correlation between the readings of these instruments and reducing dead volume and sample size requirements.

Abstract: An apparatus and associated method to begin performing a power reduction enablement sequence based on a first predetermined value of elapsed time after an execution of a data access command is completed. The power reduction enablement sequence is performed at an adaptively selected rate that is related to a second predetermined value of elapsed time after the execution that calls for a switch to a reduced power mode for the apparatus.

Abstract: A vision recognition system is provided for use with a high speed, automatic produce labeling machine. The system uses laser profiling to direct a sheet of light transversely to the longitudinal axis of a produce feed conveyor. The sheet of light periodically impacts, and generates laser profiles of, the surfaces of the produce items, such as pears, being fed by the conveyor to one or more labeling machines. The laser profiles are used to generate real world (x,y) coordinates of the domes of the incoming produce items, which are passed to the labeling machine or machines. Real world height (or z) coordinates may also be created and passed to the labeler.

Abstract: An apparatus and associated method to begin performing a power reduction enablement sequence based on a first predetermined value of elapsed time after an execution of a data access command is completed. The power reduction enablement sequence is performed at an adaptively selected rate that is related to a second predetermined value of elapsed time after the execution that calls for a switch to a reduced power mode for the apparatus.

Abstract: The invention is a truck tool box that is attached to the bed of a pickup truck. The tool box is attached using brackets, a hinge system, and a latch system that allows a user to unlatch the tool box and swing it to the user.

Abstract: The invention is a truck tool box that is attached to the bed of a pickup truck. The tool box is attached using brackets, a hinge system, and a latch system that allows a user to unlatch tile tool box and swing it to the user. A separate universal latch mount bracket for an installation of a latch allows greater variations in the placement of the latch mount bracket, while enabling the latch to be aligned with the mating latch disposed on the tool box.

Abstract: A processor is configured to perform a method (110) including a step of deriving lateral offset indicators (1062) from a longitudinal position measurement (130). Improved seek cost indicators (1063) are generated, some or all based on a respective lateral offset indicator (140). Then a target destination is selected using at least one of the improved seek cost indicators (150,160).

Abstract: A system and method for masking a boot sequence by providing a dummy processor are provided. With the system and method, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate a electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective.

Abstract: Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

Abstract: An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.

Abstract: An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.

Abstract: Page size prediction is used to predict a page size for a page of memory being accessed by a memory access instruction such that the predicted page size can be used to access an address translation data structure. By doing so, an address translation data structure may support multiple page sizes in an efficient manner and with little additional circuitry disposed in the critical path for address translation, thereby increasing performance.

Abstract: A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch history table includes multiple entries, each entry is associated with one or more branch instructions. The GBH information from the GBH buffer can be used to index into the branch history table to obtain a branch prediction signal. In response to a fetch group of instructions, a fixed number of GBH bits is shifted into the GBH buffer. The number of GBH bits is the same regardless of the number of branch instructions within the fetch group of instructions. In addition, there is a unique bit pattern associated with the case of no taken branch in the fetch group, regardless of the number of not-taken branches of even if there are any branches in the fetch group.

Abstract: A method and apparatus for efficiently storing an effective address (EA) in an effective to real address translation (ERAT) table supporting multiple page sizes by adding PSI fields, based on the number of unique page sizes supported, to each ERAT entry and using one ERAT entry to store an EA for a memory page, regardless of page size, by setting the PSI fields to indicate the page size.

Abstract: A control pedal assembly includes a support structure having a guide surface and a pedal arm carrying a pedal at a lower end of the pedal arm. The pedal arm is pivotable relative to the support structure about a pivot axis between a released position and an applied position. A hysteresis device is secured to an upper end of the pedal arm and engages the guide surface so that the hysteresis device slides along the guide surface as the pivot arm pivots between the released position and the applied position. A distance between the guide surface and the pivot axis varies so that the hysteresis device applies an increasing normal force to the guide surface to create an increasing friction force that opposes sliding motion of the hysteresis device as the pedal arm pivots from the released position to the applied position.

Abstract: A control pedal assembly includes a support structure having a guide surface and a pedal arm carrying a pedal at a lower end of the pedal arm. The pedal arm is pivotable relative to the support structure about a pivot axis between a released position and an applied position. A hysteresis device is secured to an upper end of the pedal arm and engages the guide surface so that the hysteresis device slides along the guide surface as the pivot arm pivots between the released position and the applied position. A distance between the guide surface and the pivot axis varies so that the hysteresis device applies an increasing normal force to the guide surface to create an increasing friction force that opposes sliding motion of the hysteresis device as the pedal arm pivots from the released position to the applied position.

Abstract: A processor is configured to perform a method (110) including a step of deriving lateral offset indicators (1062) from a longitudinal position measurement (130). Improved seek cost indicators (1063) are generated, some or all based on a respective lateral offset indicator (140). Then a target destination is selected using at least one of the improved seek cost indicators (150,160).

Abstract: A test circuit for exposing higher order speed paths. A test circuit includes a clock generation circuit coupled to a test clock control unit. The clock generation circuit is configured to receive an input clock signal and to generate an output clock signal. The test clock control unit is configured to selectively provide a user programmable test vector or a fixed test vector to control the generation of the output clock signal by the clock generation circuit depending upon a state of a first mode select signal.