Patents by Inventor Jason E. Stephens
Jason E. Stephens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352570Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Mark D. Levy, Sarah A. McTaggart, Laura J. Silverstein, Qizhi Liu, Jason E. Stephens
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Patent number: 11043418Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.Type: GrantFiled: November 15, 2019Date of Patent: June 22, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Lars W. Liebmann, Gregory A. Northrop
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Patent number: 10741439Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.Type: GrantFiled: May 14, 2019Date of Patent: August 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hsueh-Chung Chen, Martin J. O'Toole, Terry A. Spooner, Jason E. Stephens
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Publication number: 20200083102Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Inventors: Jason E. STEPHENS, Daniel CHANEMOUGAME, Ruilong XIE, Lars W. LIEBMANN, Gregory A. NORTHROP
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Patent number: 10522403Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.Type: GrantFiled: January 11, 2018Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Lars W. Liebmann, Gregory A. Northrop
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Publication number: 20190267281Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: Hsueh-Chung CHEN, Martin J. O'TOOLE, Terry A. SPOONER, Jason E. STEPHENS
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Publication number: 20190221474Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.Type: ApplicationFiled: January 16, 2018Publication date: July 18, 2019Inventors: Hsueh-Chung CHEN, Martin J. O'TOOLE, Terry A. SPOONER, Jason E. STEPHENS
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Publication number: 20190214298Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Jason E. STEPHENS, Daniel CHANEMOUGAME, Ruilong XIE, Lars W. LIEBMANN, Gregory A. NORTHROP
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Patent number: 10340180Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.Type: GrantFiled: January 16, 2018Date of Patent: July 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hsueh-Chung Chen, Martin J. O'Toole, Terry A. Spooner, Jason E. Stephens
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Publication number: 20190139823Abstract: One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias across substantially an entirety of an upper surface of a layer of insulating material and in the via openings. A patterned line etch mask layer is then formed above the conductive material, the etch mask having a first feature corresponding to a first conductive line and a second feature corresponding to a second conductive line, and performing at least one etching process to define the first and second conductive lines that are arranged in a tip-to-tip configuration. In this example, a first edge of the first conductive via is substantially aligned with a first end of the first conductive line and a second edge of the second conductive via is substantially aligned with a second end of the second conductive line.Type: ApplicationFiled: November 6, 2017Publication date: May 9, 2019Inventors: Hsueh-Chung Chen, Jason E. Stephens, Lars W. Liebmann, Guillaume Bouche
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Patent number: 10056373Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: GrantFiled: April 18, 2017Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Patent number: 9825031Abstract: A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.Type: GrantFiled: August 5, 2016Date of Patent: November 21, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Guillaume Bouche, Andy C. Wei, Jason E. Stephens, David M. Permana, Jagannathan Vasudevan
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Publication number: 20170221886Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Patent number: 9660040Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: GrantFiled: October 29, 2015Date of Patent: May 23, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Patent number: 9502528Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).Type: GrantFiled: August 26, 2014Date of Patent: November 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Jason E. Stephens, Tuhin Guha Neogi, Mark A. Zaleski, Andy Chih-Hung Wei
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Patent number: 9472455Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.Type: GrantFiled: April 7, 2014Date of Patent: October 18, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jason E. Stephens, Lei Yuan, Lixia Lei, David Pritchard, Tuhin Guha Neogi
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Patent number: 9461128Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.Type: GrantFiled: December 9, 2015Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
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Patent number: 9412655Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.Type: GrantFiled: January 29, 2015Date of Patent: August 9, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Guillaume Bouche, Jason E. Stephens, Vikrant Chauhan, Andy C. Wei
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Publication number: 20160225666Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.Type: ApplicationFiled: January 29, 2015Publication date: August 4, 2016Inventors: Guillaume Bouche, Jason E. Stephens, Vikrant Chauhan, Andy C. Wei
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Publication number: 20160093704Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.Type: ApplicationFiled: December 9, 2015Publication date: March 31, 2016Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche