Patents by Inventor Jason E. Stephens
Jason E. Stephens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160064514Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Inventors: Guillaume Bouche, Jason E. Stephens, Tuhin Guha Neogi, Mark A. Zaleski, Andy Chih-Hung Wei
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Publication number: 20160049481Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: ApplicationFiled: October 29, 2015Publication date: February 18, 2016Applicant: GLOBALFOUNDRIES Inc.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Patent number: 9236437Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.Type: GrantFiled: February 20, 2014Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
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Patent number: 9224617Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.Type: GrantFiled: January 29, 2014Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: David Pritchard, Jason E. Stephens
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Patent number: 9202751Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: GrantFiled: April 7, 2014Date of Patent: December 1, 2015Assignee: GlobalFoundries Inc.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Publication number: 20150287636Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
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Publication number: 20150287604Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.Type: ApplicationFiled: April 7, 2014Publication date: October 8, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Jason E. STEPHENS, Lei YUAN, Lixia LEI, David PRITCHARD, Tuhin Guha NEOGI
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Publication number: 20150236106Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Mark A. Zaleski, Andy Chih-Hung Wei, Jason E. Stephens, Tuhin Guha Neogi, Guillaume Bouche
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Publication number: 20150214064Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.Type: ApplicationFiled: January 29, 2014Publication date: July 30, 2015Applicant: Globalfoundries Inc.Inventors: David PRITCHARD, Jason E. STEPHENS
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Patent number: 8839168Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.Type: GrantFiled: January 22, 2013Date of Patent: September 16, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jongwook Kye, Harry J Levinson, Jason E Stephens, Lei Yuan
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Patent number: 8793627Abstract: Methodology enabling designs with a reduced V0 distance to M1 inner vertex restriction is disclosed. Embodiments include determining a limiting parameter ? for manufacture of an SAV proximate to an M1 inner vertex; defining a coordinate system in terms of horizontal and vertical distances x and y, respectively, between the SAV and the M1 inner vertex angle; calculating ? as a function of x and y; simulating the calculation of ? as a function of x and y; calculating a baseline angle ?1 as a function of x and y; simulating calculation of the baseline angle ?1 as a function of x and y; extracting a 3? value of the baseline angle ?1 from the simulation; and designing a semiconductor cell with an SAV proximate to an M1 inner vertex, the cell having a limiting parameter ? minimum value equal to the 3? value of the baseline angle ?1.Type: GrantFiled: March 15, 2013Date of Patent: July 29, 2014Assignee: GlobalFoundries Inc.Inventors: Jason E. Stephens, Marc Tarabbia
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Publication number: 20140208285Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Jongwook Kye, Harry J. Levinson, Jason E. Stephens, Lei Yuan
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Patent number: 8598633Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.Type: GrantFiled: January 16, 2012Date of Patent: December 3, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130181289Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.Type: ApplicationFiled: January 16, 2012Publication date: July 18, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan