Patents by Inventor Jason G. Sandri
Jason G. Sandri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11620398Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.Type: GrantFiled: May 29, 2019Date of Patent: April 4, 2023Assignee: INTEL CORPORATIONInventors: Neeraj S. Upasani, David P. Turley, Sergiu D. Ghetie, Zhangping Chen, Jason G. Sandri
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Publication number: 20190278932Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.Type: ApplicationFiled: May 29, 2019Publication date: September 12, 2019Applicant: INTEL CORPORATIONInventors: NEERAJ S. UPASANI, DAVID P. TURLEY, SERGIU D. GHETIE, ZHANGPING CHEN, JASON G. SANDRI
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Patent number: 10318748Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.Type: GrantFiled: September 30, 2016Date of Patent: June 11, 2019Assignee: INTEL CORPORATIONInventors: Neeraj S. Upasani, David P. Turley, Sergiu D. Ghetie, Zhangping Chen, Jason G. Sandri
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Publication number: 20180167199Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventors: Himanshu Kaul, Sanu K. Mathew, Mark A. Anders, Jesse Walker, Jason G. Sandri
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Publication number: 20180095897Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Applicant: INTEL CORPORATIONInventors: NEERAJ S. UPASANI, DAVID P. TURLEY, SERGIU D. GHETIE, ZHANGPING CHEN, JASON G. SANDRI
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Patent number: 9922720Abstract: In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device.Type: GrantFiled: March 7, 2013Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Jason G. Sandri, Horaira Abu, Charles A. Peterson, Matthew B. Pedersen, Brian Harris, Ian S. Walker, Monib Ahmed
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Patent number: 9472302Abstract: In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.Type: GrantFiled: March 7, 2013Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Jason G. Sandri, Steve J. Brown, Peter R. Munguia, Monib Ahmed, Adrian R. Pearson
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Patent number: 9292713Abstract: In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.Type: GrantFiled: March 13, 2013Date of Patent: March 22, 2016Assignee: Intel CorporationInventors: Jason G. Sandri, Monib Ahmed, Ian S. Walker
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Patent number: 8971137Abstract: In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output.Type: GrantFiled: March 7, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Jason G. Sandri, Ian S. Walker, Monib Ahmed
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Patent number: 8923030Abstract: In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.Type: GrantFiled: March 7, 2013Date of Patent: December 30, 2014Assignee: Intel CorporationInventors: Jason G. Sandri, Ian S. Walker, Monib Ahmed
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Publication number: 20140283119Abstract: In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Jason G. Sandri, Monib Ahmed, Ian S. Walker
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Publication number: 20140254296Abstract: In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Jason G. Sandri, Ian S. Walker, Monib Ahmed
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Publication number: 20140254233Abstract: In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Jason G. Sandri, Steve J. Brown, Peter R. Munguia, Monib Ahmed, Adrian R. Pearson
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Publication number: 20140254234Abstract: In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Jason G. Sandri, Horaira Abu, Charles A. Peterson, Matthew B. Pedersen, Brian Harris, Ian S. Walker, Monib Ahmed
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Publication number: 20140253221Abstract: In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Jason G. Sandri, Ian S. Walker, Monib Ahmed
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Patent number: 8799728Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: October 25, 2013Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8745455Abstract: In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.Type: GrantFiled: November 23, 2010Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Ruben Ramirez, Michael J. Wiznerowicz, Sean T. Baartmans, Jason G. Sandri
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Publication number: 20140053026Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Inventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8589745Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: December 11, 2012Date of Patent: November 19, 2013Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8543776Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: October 31, 2012Date of Patent: September 24, 2013Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger