Abstract: The invention generally relates to an improved processes for the preparation of a cyclic dinucleotide which is useful as a STING agonist of the following formula (I), involving the use of compounds A and B.

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

Abstract: In one aspect, evaporator boats are provided which, in some embodiments, exhibit resistance to corrosion and associated performance degradation imparted by exposure to molten metals, including aluminum. An evaporator boat described herein comprises a body and an evaporator surface, the body comprising a boron nitride (BN) component and a TiB2 component including a solid solution of TiB2 and one or more elements selected from the group consisting of silicon and metallic elements of Groups IVB-VIIIB of the Periodic Table.

Abstract: The present invention is directed to cyclobutyl pyrazolopyrimidine compounds which may be useful as therapeutic agents for the treatment of disorders associated with phosphodiesterase 9 (PDE9). The present invention also relates to the use of such compounds for treating cardiovascular and cerebrovascular diseases, such as hypertension, chronic kidney disease and heart failure, and neurological and psychiatric disorders, such as schizophrenia, psychosis or Huntington's disease, and those associated with striatal hypofunction or basal ganglia dysfunction.

Abstract: Disclosed are compounds of Formula (I), Formula (II), or a salt thereof: Formula (I) Formula (II) which compounds have properties for inhibiting Nav 1.7 ion channels found in peripheral and sympathetic neurons. Also described are pharmaceutical formulations comprising the compounds of Formula (I), Formula (II) or their salts, and methods of treating pain disorders, cough, and itch using the same.

Abstract: Disclosed herein are engineered latent guide RNAs targeting LRRK2 and compositions comprising the same for treatment of diseases or conditions (e.g. Parkinson's Disease) in a subject. Also disclosed herein are methods of treating diseases or conditions (e.g. Parkinson's Disease) in a subject by administering engineered latent guide RNAs or pharmaceutical compositions described herein.

Abstract: Provided herein are compounds, and pharmaceutically acceptable salts thereof, useful as KRAS inhibitors, methods of making and using the same (singly or in combination with additional agents), and pharmaceutical compositions thereof.

Abstract: A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.

Abstract: A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.

Abstract: Methods and apparatuses for preventing the unauthorized use and display of sensitive information contained within search results or within documents that are linked to by search results or electronic messages are described. A permissions-aware search and knowledge management system may continuously scan the content of documents and messages indexed by the system and detect that a document shared by link contains sensitive information. In response to detecting that the document has been accessed by at least a first number of different users or has the ability to be accessed by at least a second number of different users, the permissions-aware search and knowledge management system may adjust file permissions, adjust access control lists, selectively disable links to the document, and/or perform content redactions for the document such that some system users do not have the ability to view or access the sensitive information within the document.

Abstract: A memory device includes memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, where n is a whole number larger than two, and a periphery circuit coupled to the memory cells and configured to program selected memory cells according to n logic pages of current programming data. The periphery circuit includes page buffers, and each page buffer includes latches.

Abstract: A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.

Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.

Abstract: A system includes multiple memory dies. Each of the memory dies includes a PPM circuit including a first pull driver, a second pull driver, and a PPM contact pad connected between the first pull driver and the second pull driver. The PPM contact pads of the multiple memory dies are electrically connected with each other. The PPM circuits of the multiple memory dies are configured to manage peak power operations according to a first pull current flowing through a certain first pull driver of a certain PPM circuit. The first pull current is a sum of second pull currents flowing through second pull drivers of the PPM circuit. Each of the second pull currents is proportional to a current level of a corresponding memory die.

Abstract: A method of peak power management (PPM) for a storage system with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the storage system; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the storage system is less than a maximum total current allowed for the storage system.

Abstract: Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

Abstract: Systems and methods for changing broadcast channels using channel change requests to, and channel change responses from, an SDV server. In some embodiments, the channel change request is made after determining that broadcast tuning parameters are otherwise not available from memory and/or a broadcast system.

Abstract: Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding a lower page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The page buffers include the first, second and third sets of data latches configured to store the lower page, a middle page and an upper page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the second set of data latches after the discarding the middle page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.

Abstract: Signal correction circuitry is described that improves the integrity of data transmitted over a serial data interface without interrupting the communication between the connected devices. The signal correction circuitry includes edge correction circuitry that speeds up the rising and falling edges of the data signal(s). The signal correction circuitry also includes DC compensation circuitry that boosts the level(s) of the data signal(s).