Abstract: Generally, this disclosure provides circuits and methods to reduce and regulate DC link voltage in a power supply through the use of a DC breaker circuit. The breaker circuit may include a breaker switch configured to couple an input stage circuit of a power supply to an output stage circuit of the power supply and to provide a regulated DC link voltage to the output stage circuit, the level of the DC link voltage based on switching states of the breaker switch. The breaker circuit may further include a control circuit configured to generate a gate control signal to control the switching states of the breaker switch, the gate control signal based on a comparison of the DC link voltage to a high voltage threshold and a low voltage threshold, such that the magnitude of the DC link voltage is regulated to a set point and a peak-to-peak ripple.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel processing sequence to form a solar cell device. Methods of forming the high efficiency solar cell may include the use of a prefabricated back plane that is bonded to the metalized solar cell device to form an interconnected solar cell module. Solar cells most likely to benefit from the invention including those having active regions comprising single or multicrystalline silicon with both positive and negative contacts on the rear side of the cell.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.

Abstract: A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: A decoding system for multi-plane memories routes address information corresponding to distinct memory access operations to the designated planes. The system includes an array of functional registers dedicated to random access read, burst read, program, erase, and erase-suspend program operations. Plane selector blocks for each plane receive the address outputs from all of the registers and plane function select logic controls the routing in accord with memory access commands for specified planes. Simultaneous operations of different type in different planes and nested operations in the same plane are possible.

Abstract: In a non-volatile memory, a programming cycle consists of the following phases: high voltage charging up, programming pulse, and discharge. The actual programming process only takes place in the programming pulse phase. Several break points are defined relative to elapsed time and introduced in the programming pulse phase. Upon receiving a suspend request, the programming operation will advance to the next break point, then discharge the high programming voltage and go to a suspend state. A separate counter is used to monitor the break points so that elapsed non-programming time can be deducted from the total programming pulse time when the programming operation is resumed. By doing so, the device can handle frequent suspend and resume requests. Since the total time duration in the programming pulse phase is equal for the programming operation with and without suspend and resume requests, the programming proceeds efficiently to completion.

Abstract: A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding.

Abstract: A multi-phase power supply utilizes a current sensor including a sensor inductor winding connected in parallel with a filter inductor winding at the output of each phase for sensing the phase currents and balancing the current by adjusting the duty cycle of each phase through feedback control. In addition, in a multi-module power supply configuration, current between power supply modules is balanced through use of the same current sensor and current sharing technique. Each phase of the power supply includes at least one input power source and a current sensor. The sensor inductor winding and the filter inductor winding have the same number of turns and are wound about a magnetic core also present at each phase. A differential amplifier at each phase senses and amplifies any voltage difference between the outputs of the sensor inductor winding and the corresponding filter inductor winding.