Abstract: Using a bounding language to control or restrict the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”), and also the bounding language and documents encoded according to the bounding language. A Document Type Definition (“DTD”) is defined as a “bounding DTD”, and one or more structured documents containing editing restrictions are defined according to this DTD. A processing component uses a structured document containing editing restrictions as input, and programmatically determines which fields of another structured document can be edited, which fields should be hidden, and so forth. By restricting the parts of the file that can be edited, users who need to do the editing are shielded from irrelevant details, and can carry out their task with less risk of making errors (and without needing to understand the details of the structured document markup language).

Abstract: Methods, systems, computer program products, and methods of doing business by using a meta-editor to generate components (e.g., a specification of a rules language that restricts editing operations on structured documents, a specification of rules according to this language, and a graphical user interface editor that operates according to the specified rules) for use in controlling or restricting the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”). A Document Type Definition (“DTD”) is generated as a “bounding DTD”, based on editing choices made using the meta editor, and one or more structured documents containing editing restrictions are generated according to this DTD and these editing choices. An editor (or editing component) is generated that programmatically determines which elements of another structured document can be edited, which elements should be hidden, and so forth.

Abstract: Methods, systems, computer program products, and methods of doing business by using a bounding language to control or restrict the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”), and also includes the bounding language and documents encoded according to the bounding language. A Document Type Definition (“DTD”) is defined as a “bounding DTD”, and one or more structured documents containing editing restrictions are defined according to this DTD. A processing component uses a structured document containing editing restrictions as input, and programmatically determines which fields of another structured document can be edited, which fields should be hidden, and so forth.

Abstract: Methods, systems, computer program products, and methods of doing business by using a meta-editor to generate components (e.g., a specification of a rules language that restricts editing operations on structured documents, a specification of rules according to this language, and a graphical user interface editor that operates according to the specified rules) for use in controlling or restricting the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”). A Document Type Definition (“DTD”) is generated as a “bounding DTD”, based on editing choices made using the meta editor, and one or more structured documents containing editing restrictions are generated according to this DTD and these editing choices. An editor (or editing component) is generated that programmatically determines which elements of another structured document can be edited, which elements should be hidden, and so forth.

Abstract: A memory device having a plurality of data paths connected between a main memory by a plurality of data pads. Each of the data path transfers a first and second data bits from the main memory to a data pad in one clock cycle during a read operation. The first data bit is transferred to the data pad in a shorter path than the path of the second data bit.

Abstract: A clock buffer circuit (100) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section (102) drives to a first output node (114) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section (108) and clock generator (106) are provided. In response to low-to-high transitions at the first output node (114) the pulse generator (106) generates a pulse at a pulse output (126). In response to the pulse, the boost section (108) provides additional driving capability for further pulling the first output node (114) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit (104) provides the CLKI signal in response to the CLKI_ signal. An enabling section (110) is provided for enabling, or alternatively, disabling the preferred embodiment (100).

Abstract: A circuit is designed with a delay circuit (300) coupled to receive a clock input signal (CLK) and a control signal (DFT). The control signal has a first logic state and a second logic state. The delay circuit produces a clock control signal (*CLK) at a first time in response to the first logic state and at a second time in response to the second logic state. A clock circuit (200) is coupled to receive the clock input signal and is enabled by the clock control signal. The clock circuit produces a first clock pulse signal having a predetermined width in response to a first transition of the clock input signal and produces a second clock pulse signal having the predetermined width in response to a second transition of the clock input signal.

Abstract: A device is discussed that enables an input buffer to recognize the first rising edge of a strobe so as to validate data. In one embodiment, a method for enabling recognition of valid data in a DDR SDRAM is discussed. The method includes analyzing memory commands before a setup time is expired, and validating the data to input into the DDR SDRAM when the act of analyzing memory commands enables a circuit to recognize the first rising edge of a strobe so as to validate the data. In another embodiment, a device for enabling validation of data in a DDR SDRAM is discussed. The device includes an analyzer to analyze commands to produce a write signal, and an enabling circuit to produce an enabling signal before the write signal is confirmed to recognize a first rising edge of a strobe so as to validate the data.

Abstract: A redundancy circuit (300) for generating a standard column access signal (STD) and a redundant column access signal (RED) is disclosed. A modified NOR-type decoder (310) determines if an applied address is the same as a defective address. In the event the applied address is the same as the defective address, a match indication is activated. In the event the applied address is different than the defective address, a no match indication is generated. The match indication activates the RED signal and the no match indication activates the STD signal, according to the timing of a "mimic" circuit (312). The mimic circuit (312) emulates the slowest resolution of the match/no match indication by the modified NOR-type decoder (310).