Abstract: A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device.

Abstract: A counting circuit for a data processing apparatus has a normal mode in which a main counter increments the time count value in response to edges of a main clock signal, and a power saving mode in which the main clock signal is disabled and a further clock counter counts elapsed edges of a further clock signal having a lower frequency than the main clock signal. On switching to power saving mode, a reference time count value of the main counter is captured at a timing triggered by an edge of the further clock signal. On switching back to normal mode, an expected time count value from the main counter is calculated based on the captured reference value and the counted number of elapsed edges during the power saving mode, and the main counter is restarted at a timing triggered by another edge of the further clock signal.

Abstract: A counting circuit for a data processing apparatus has a normal mode in which a main counter increments the time count value in response to edges of a main clock signal, and a power saving mode in which the main clock signal is disabled and a further clock counter counts elapsed edges of a further clock signal having a lower frequency than the main clock signal. On switching to power saving mode, a reference time count value of the main counter is captured at a timing triggered by an edge of the further clock signal. On switching back to normal mode, an expected time count value from the main counter is calculated based on the captured reference value and the counted number of elapsed edges during the power saving mode, and the main counter is restarted at a timing triggered by another edge of the further clock signal.

Abstract: Managing electrocardiogram (ECG) processing is described. ECGs are distributed to a technician system and/or a cardiologist system based on protocol data and one or more factors to promote processing efficiency for the ECGs. A modification to the protocol data can be received. Processed ECGs can be analyzed in view of the modification to identify ECGs for reprocessing. The identified ECGs can be reprocessed in accordance with the modification to the protocol data and, if applicable, the factors.

Abstract: Managing electrocardiogram (ECG) processing is described. ECGs are distributed to a technician system and/or a cardiologist system based on protocol data and one or more factors to promote processing efficiency for the ECGs. A modification to the protocol data can be received. Processed ECGs can be analyzed in view of the modification to identify ECGs for reprocessing. The identified ECGs can be reprocessed in accordance with the modification to the protocol data and, if applicable, the factors.

Abstract: The invention relates to a method for improving caching efficiency in a computing device. It utilises metadata, that describes attributes of the data to which it relates, to determine an appropriate caching strategy for the data. The caching strategy may be based on the type of the data, and/or on the expected access of the data.

Abstract: According to various embodiments of the present invention, a data management process is provided that manages ECG data collection, review, and reporting in an efficient and secure manner by utilizing biometric checks, quality control measures, and workflow control systems that route data based on a variety of factors to efficiently complete the measurement and analysis process.

Abstract: According to various embodiments of the present invention, a data management process is provided that manages ECG data collection, review, and reporting in an efficient and secure manner by utilizing biometric checks, quality control measures, and workflow control systems that route data based on a variety of factors to efficiently complete the measurement and analysis process.

Abstract: A method and system for creating a quiet zone. In an exemplary embodiment, the method includes receiving a request for the creation of the quiet zone and generating a quiet time data packet. The quiet time data packet may be generated by a source system and includes data specifying the start and duration of the quiet time. The quiet time data packet is transmitted from the source system to at least one destination system. Upon receipt of the quiet time data broadcast, the at least one destination system implements a quiet time for the specified duration within the destination system environment.

Abstract: A user friendly display interface system for simplifying the user interactive display interface through removal of inactive windows comprising the combination of an implementation for determining whether each of said plurality of windows is active, an implementation for presetting an initial time period for which each of said plurality of windows may remain inactive and means responsive to the end of said initial time period for each of the plurality of windows for commencing a time-out period for each of the plurality of windows. There is a display indicator for the progress of this time-out period towards termination for any windows, together with an implementation for each of the plurality of windows for closing said window upon termination of its time-out period. There is also a user interactive implementation for restoring any of the plurality of windows to active during said time-out period.

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor. These devices are particularly suitable for incorporation in optical and opto-electronic intergrated circuits as they permit the fabrication of waveguides having right-angle bends with a radius of the order of 2 ?m.

Abstract: There is provided a non-linear optical device for enhancing the bandwidth accessible in the nonlinear generation of an optical signal. The device comprises a planar optical waveguide, the planar optical waveguide being operative to generate an optical output from an optical input having an input bandwidth by means of a non-linear optical process, the optical output having a wavelength within an accessible bandwidth, wherein the planar optical waveguide is operative to enhance the accessible bandwidth such that the ratio of the accessible bandwidth to the input bandwidth is at least 4. The device is particularly applicable to broad optical continuum generation, but may also be used in a parametric oscillator or amplifier arrangement with broad tuning range.

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor. These devices are particularly suitable for incorporation in optical and opto-electronic integrated circuits as they permit the fabrication of waveguides having right-angle bends with a radius of the order of 2 &mgr;m.

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor.

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor. These devices are particularly suitable for incorporation in optical and opto-electronic integrated circuits as they permit the fabrication of waveguides having right-angle bends with a radius of the order of 2 &mgr;m.

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor.

Abstract: The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether “in-line” inspection data can account for a given failure.