Abstract: A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition is formed at the minor surface of the substrate. The eutectic alloy composition is removed from the minor surface of the substrate such that a portion of the eutectic alloy composition remains at an outer perimeter of the minor surface to strengthen the outer perimeter of the substrate. A bonding layer is deposited over the minor surface and over the portion of the eutectic alloy composition at the outer perimeter of the minor surface. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. Additional eutectic alloy composition may remain on the minor surface of the substrate at the streets to strengthen the substrate during device wafer separation.

Abstract: A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition is formed at the minor surface of the substrate. The eutectic alloy composition is removed from the minor surface of the substrate such that a portion of the eutectic alloy composition remains at an outer perimeter of the minor surface to strengthen the outer perimeter of the substrate. A bonding layer is deposited over the minor surface and over the portion of the eutectic forming alloy composition at the outer perimeter of the minor surface. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. Additional eutectic alloy composition may remain on the minor surface of the substrate at the streets to strengthen the substrate during device wafer separation.

Abstract: In making electronic component packages, a method includes forming a sacrificial material over a first temporary substrate, applying a second temporary substrate to the sacrificial material, and then curing the sacrificial material. After curing, the second temporary substrate is removed. The top surface of the sacrificial layer is defined by the second temporary substrate. After removal, a redistribution structure is formed on the top surface. After the formation of the redistribution structure, electronic components are applied to the redistribution structure. The electronic components are encapsulated to form an encapsulated panel. The first temporary substrate and the sacrificial material are removed. The panel is singulated into multiple electronic component packages.

Abstract: In making electronic component packages, a method includes forming a sacrificial material over a first temporary substrate, applying a second temporary substrate to the sacrificial material, and then curing the sacrificial material. After curing, the second temporary substrate is removed. The top surface of the sacrificial layer is defined by the second temporary substrate. After removal, a redistribution structure is formed on the top surface. After the formation of the redistribution structure, electronic components are applied to the redistribution structure. The electronic components are encapsulated to form an encapsulated panel. The first temporary substrate and the sacrificial material are removed. The panel is singulated into multiple electronic component packages.

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: A method for making an electronic component package from an encapsulated panel. The encapsulated panel includes two packaging substrate assembles including electronic components. Access sides of the electronic components face outward from the encapsulated panel. Standoffs separate the packaging substrate assemblies from each other.

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Abstract: A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.

Abstract: Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

Abstract: Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.