Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Abstract: The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation. Thus, one set of pins may be used for various different I/O devices.

Abstract: The present invention provides a system and method for introducing white noises into a digital audio signal so that there is progressive and cumulative degradation in audio quality after each successive reproduction of the audio sound signal in a fashion analogous to analog audio reproduction. The invention provides a white noise generator, and a digital entroping unit. In a preferred embodiment, the white noise generator is implemented by a hardware random number generator. The digital entroping unit controls the magnitude of white noise desired based on a random number generated by the random number generator, and adds the white noise to the input audio sound signal to produce a degraded audio sound signal. The magnitude of white noise can be controlled by using various masking and formatting of random number data.

Abstract: Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device; pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.

Abstract: A headset phone for use with an audio system. A conventional 4-tap, combo phone connector is provided that has a sleeve tap, a tip tap, a first ring tap, and a second ring tap. A first speaker element is connected across the sleeve and tip taps and a second speaker element is connected across the sleeve and first ring taps. A microphone is connected across the sleeve and second ring tap. At least one control unit, other than a mute control, is also connected across the sleeve and second ring taps, such that operation of any control unit changes the impedance across the sleeve and second ring tap that is seen by the audio system.

Abstract: A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.

Abstract: Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device;pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.

Abstract: A circuit for use in powering a load having dynamic power needs. A variable strength controller is provided that has a feedback terminal, at least one p-terminal, and at least one n-terminal. The p? and n-terminals are each suitable for driving a respective semiconductor device to partially control the power to the load as the said feedback terminal receives a feedback signal representative of actual demand for the power by the load. A total of at least three p? and n-terminals are provided, and their selective employment thus collectively fully controls the power to the load.

Abstract: The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation, such as tri-state I/O devices, pull-up I/O devices, or pull-down I/O devices. Thus, one set of pins may be used for various different I/O devices.

Abstract: The present invention provides a system and method for introducing white noises into a digital audio signal so that there is progressive and cumulative degradation in audio quality after each successive reproduction of the audio sound signal in a fashion analogous to analog audio reproduction. The invention provides a white noise generator, and a digital entroping unit. In a preferred embodiment, the white noise generator is implemented by a hardware random number generator. The digital entroping unit controls the magnitude of white noise desired based on a random number generated by the random number generator, and adds the white noise to the input audio sound signal to produce a degraded audio sound signal. The magnitude of white noise can be controlled by using various masking and formatting of random number data.

Abstract: A power management system and method permit the total power consumption by a portable electronic device to be reduced so that the portable electronic device has a longer operating time on a limited power source, such as a battery. The system may also be used with devices that are powered by a more permanent source of power. The system may combine static power management techniques as well as dynamic power management techniques. The system may include a flexible clock generator.

Abstract: An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level. The interrupt handling system also permits software based interrupts wherein, for example, one processor may interrupt another processor.

Abstract: To facilitate inter-processor communication between multiple processors in a computer system and to enable the accessing of a dual port memory, or other system resources, without requiring the memory or the data/address bus to be locked, the present invention provides a semaphore unit that preferably incorporates a shared mailbox architecture that, in combination with a set of hardware semaphore registers, enables inter-process communication among the multi-processors. Cooperative multitasking may be accomplished through the use of shared mailbox communication protocols while a preemptive multitasking may be accomplished through the use of hardware semaphore registers.

Abstract: The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplexor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle.

Abstract: A random number generation system and method use the randomness in hardware circuitry start-up to generate a random seed for a random number. In a preferred embodiment, the instability of a phase locked loop is used.

Abstract: The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplxor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle.

Abstract: The present invention provides a system and method for introducing white noises into a digital audio signal so that there is progressive and cumulative degradation in audio quality after each successive reproduction of the audio sound signal in a fashion analogous to analog audio reproduction. The invention provides a white noise generator, and a digital entroping unit. In a preferred embodiment, the white noise generator is implemented by a hardware random number generator. The digital entroping unit controls the magnitude of white noise desired based on a random number generated by the random number generator, and adds the white noise to the input audio sound signal to produce a degraded audio sound signal. The magnitude of white noise can be controlled by using various masking and formatting of random number data.