Abstract: A power management system and method permit the total power consumption by a portable electronic device to be reduced so that the portable electronic device has a longer operating time on a limited power source, such as a battery. The system may also be used with devices that are powered by a more permanent source of power. The system may combine static power management techniques as well as dynamic power management techniques. The system may include a flexible clock generator.

Abstract: A cross bar multipath resource controller system and method permit multiple processors in a computer system to access various resource of the computer system, such as memory or peripherals, with zero blocking access. In particular, each processor has its own bus so that the processors can each independently access different resources in the computer system simultaneously.

Abstract: An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level. The interrupt handling system also permits software based interrupts wherein, for example, one processor may interrupt another processor.

Abstract: To facilitate inter-processor communication between multiple processors in a computer system and to enable the accessing of a dual port memory, or other system resources, without requiring the memory or the data/address bus to be locked, the present invention provides a semaphore unit that preferably incorporates a shared mailbox architecture that, in combination with a set of hardware semaphore registers, enables inter-process communication among the multi-processors. Cooperative multitasking may be accomplished through the use of shared mailbox communication protocols while a preemptive multitasking may be accomplished through the use of hardware semaphore registers.

Abstract: A software-based direct memory access (DMA) engine for a multiple processor system eliminates the overhead and limitations associated with conventional hardware DMA engines. In a preferred embodiment, the DMA engine is implemented in a two processor system that includes separate processor buses and uses a store multiple data locations instruction in combination with a load multiple data locations instruction.

Abstract: A random number generation system and method use the randomness in hardware circuitry start-up to generate a random seed for a random number. In a preferred embodiment, the instability of a phase locked loop is used.

Abstract: The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation, such as tri-state I/O devices, pull-up I/O devices, or pull-down I/O devices. Thus, one set of pins may be used for various different I/O devices.

Abstract: A multimedia console keyboard provides a convenient user interface to provide multimedia functions easily accessible to the user. In general, the multimedia console keyboard provides speakers, microphones, volume control, brightness control, contrast control, a pointing device, an electronic keyboard template with contact sensitive ICON and a real time clock/calendar alarm and computer power control switch at the keyboard. The multimedia console keyboard provides an integrated analog-digital preprocessor with audio compression and expansion capabilities and other analog capabilities. Integrated audio allows for a closed-loop voice activation and control for the computer.

Abstract: A method and apparatus using a virtual addressing buffer circuit afford address mapping and control flexibility to provide a unique opportunity for device emulation and software debugging. The method permits the emulation of a device which is physically not present in a CPU controlled system utilizing a virtual addressing buffer circuit. The method includes the step of storing a match address which corresponds to an address location of the device. The virtual addressing buffer intercepts an address request from a CPU for the address location of the device. Bits of the requested address which are not relevant to a determination of whether the requested address matches the match address are filtered out to produce a filtered request address. The filtered request address is compared with the match address, and a match indicator is activated when the filtered requested address matches the match address.

Abstract: A rule-based DRAM controller asserts memory access and control signals (including the CAS, RAS, WE, and address data signals) based upon pre-specified control rules. Certain pre-specified rules, or conditions, are used by the DRAM controller to determine the timing and sequence of the memory accessing and control signals output by the DRAM controller. The control rules for asserting the various memory accessing signals are advantageously implemented as logic within the DRAM controller, while the conditions and qualification for the control rules are provided from various monitoring signals and independently operating timing modules which keep track of the DRAM and controller states. Based upon these rules and conditions, the request inputs to the DRAM controller are interpreted to provide optimum access speed to the DRAM.