Abstract: This provides an improved process for making a flexible, porous, dissolvable solid sheet article with improved pore structures.

Abstract: A bitter masking agent includes a biochelant and a salt. A composition for an additive to reduce bitterness includes a chelant sodium salt including an aldonic, uronic, or aldaric acid. The bitter masking agent or additive comprising the biochelant and the salt can be combined with an edible material to reduce the bitterness thereof.

Abstract: Aspects of the present disclosure relate to optimization of packet processing when packets are received out of order in sequence. For example, a user equipment (UE) may determine whether a difference between a sequence number of a first packet and a sequence number of a second packet received subsequent to receiving the first packet exceeds a sequence jump threshold. The UE may disregard the second packet from processing in response to at least determining that the difference is greater than the sequence jump threshold. The UE may receive and process a plurality of packets respectively associated with a plurality of sequence numbers that are greater than the sequence number of the first packet and less than the sequence number of the second packet.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a method may include simulating a degradation of at least one of a first wireless communication link with a network or a different second wireless communication link with the network based on detecting that a first set of one or more packets, which were received via the first wireless communication link with the network and were added to a packet buffer, and a second set of one or more packets, which were received via the different second wireless communication link with the network and were added to the packet buffer, satisfy a threshold occupancy of the packet buffer. Numerous other aspects are provided.

Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a method may include simulating a degradation of at least one of a first wireless communication link with a network or a different second wireless communication link with the network based on detecting that a first set of one or more packets, which were received via the first wireless communication link with the network and were added to a packet buffer, and a second set of one or more packets, which were received via the different second wireless communication link with the network and were added to the packet buffer, satisfy a threshold occupancy of the packet buffer. Numerous other aspects are provided.

Abstract: Methods, systems, and devices for wireless communications are described. A receiving device may receive, at a first operational layer of the receiving device, one or more protocol data units (PDUs) within a set of PDUs. The receiving device may identify, at a second operational layer of the receiving device, a sequence gap associated with a missing PDU from the set of PDUs, the first operational layer being a lower operational layer of the receiving device than the second operational layer. The receiving device may determine, at the second operational layer, that a triggering condition associated with the missing PDU has occurred. The receiving device may provide, by the second operational layer and based at least in part on the triggering condition occurring, an indication to update a reception buffer of the first operational layer to a last received protocol data unit of the set of PDUs.

Abstract: Methods, systems, and devices for wireless communications are described. A receiving device may receive, at a first operational layer of the receiving device, one or more protocol data units (PDUs) within a set of PDUs. The receiving device may identify, at a second operational layer of the receiving device, a sequence gap associated with a missing PDU from the set of PDUs, the first operational layer being a lower operational layer of the receiving device than the second operational layer. The receiving device may determine, at the second operational layer, that a triggering condition associated with the missing PDU has occurred. The receiving device may provide, by the second operational layer and based at least in part on the triggering condition occurring, an indication to update a reception buffer of the first operational layer to a last received protocol data unit of the set of PDUs.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog high gain transistor includes a double well, which includes the well implants of the low voltage (LV) and intermediate voltage (IV) transistors. In addition, the analog high gain transistor includes light doped extension regions of IV transistor and a thin gate dielectric of the LV transistor.

Abstract: Non-volatile (NV) Multi-time programmable (MTP) memory cells are presented. The memory cell includes a substrate and first and second wells in the substrate. The memory cell includes first transistor having a select gate, second transistor having a floating gate adjacent to one another and on the second well, and third transistor having a control gate on the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and second wells. The transistors include first and second diffusion regions disposed adjacent to sides of the gates. The first and second diffusion regions include base lightly doped drain (LDD) and halo regions. One of the first and second diffusion regions of one of the second and third transistors includes second LDD and halo regions having higher dopant concentrations than the base LDD and halo regions.

Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.

Abstract: Methods and compounds effective in ameliorating conditions characterized by unwanted calcium channel activity, particularly unwanted T-type calcium channel activity are disclosed. Specifically, a series of compounds containing N-piperidinyl acetamide derivatives as shown in formula (1).

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.

Abstract: A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.

Abstract: Methods and compounds effective in ameliorating conditions characterized by unwanted calcium channel activity, particularly unwanted T-type calcium channel activity are disclosed. Specifically, a series of compounds containing N-piperidinyl acetamide derivatives as shown in formula (1).

Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

Abstract: A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.