Abstract: One embodiment provides an apparatus for fluorescence lifetime imaging (FLI). The apparatus includes a deep neural network (DNN). The DNN includes a first convolutional layer, a plurality of intermediate layers and an output layer. The first convolutional layer is configured to receive FLI input data. Each intermediate layer is configured to receive a respective intermediate input corresponding to an output of a respective prior layer. Each intermediate layer is further configured to provide a respective intermediate output related to the received respective intermediate input. The output layer is configured to provide estimated FLI output data corresponding to the received FLI input data. The DNN is trained using synthetic data.

Abstract: Provided herein are systems comprising one or both of cytokines and/or synthetic pathway activators. Also provided herein are systems comprising one or more suppressors of gene expression, and one or both of cytokines and/or synthetic pathway activators. Also provided are systems of chimeric priming receptors that bind ALPG and/or ALPP, chimeric antigen receptors that bind MSLN, and at least one of one or more suppressors of gene expression, and/or one or both of cytokines and/or synthetic pathway activators; cells expressing such systems; and methods of use thereof.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures.

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

Abstract: A method of measuring edema (e.g., peripheral edema and/or lymphedema) is described. The method involves directing a pulse of compressed air or other gas at a skin surface and determining the level of edema using processed camera images of the skin surface after indentation with the compressed air or other gas. The method can be completed within minutes, is simple to perform, and is free of user bias. Devices and systems for measuring edema and/or one or more skin-related properties are also described. The devices can be portable and suitable for use in medical or veterinary settings as well as for in-home/personal use.

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.

Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.

Abstract: An electrical connector having a squib connector and a squib assembly for mating by moving them together in a mating direction. A retaining means is provided for retaining the squib connector and squib assembly in a fully mated condition. A spring, acting in a direction opposite the mating direction, provides a resisting force to oppose mating. During the application of a mating force to overcome the resisting force of the spring and move the squib connector and squib assembly in the mating direction, and prior to the squib connector and squib assembly reaching the fully mated condition, removal of the resisting force of the spring is triggered and the mating force is instantly applied to moving the squib connector and squib assembly to the fully mated condition, whereat the retaining means is activated. The spring is molded to have features that assure dependable operation of the connector.

Abstract: An electrical connector having a squib connector and a squib assembly for mating by moving them together in a mating direction. A retaining means is provided for retaining the squib connector and squib assembly in a fully mated condition. A spring, acting in a direction opposite the mating direction, provides a resisting force to oppose mating. During the application of a mating force to overcome the resisting force of the spring and move the squib connector and squib assembly in the mating direction, and prior to the squib connector and squib assembly reaching the fully mated condition, removal of the resisting force of the spring is triggered and the mating force is instantly applied to moving the squib connector and squib assembly to the fully mated condition, whereat the retaining means is activated. The spring is molded to have features that assure dependable operation of the connector.

Abstract: Embodiments of a multi-stage spring system are provided herein. In some embodiments, a multi-stage spring system includes a spring assembly having at least one resilient element, wherein the spring assembly has a first spring constant when deflected up to a first distance, a greater, second spring constant when deflected beyond the first distance and up to a second distance, and a greater, third spring constant when deflected beyond the second distance and up to a third distance, and wherein the spring assembly stores mechanical energy when deflected towards a contact surface that biases the spring assembly away from the contact surface when released.

Abstract: Embodiments of the present invention provide microelectromechanical systems (MEMS) switching methods and apparatus having improved performance and lifetime as compared to conventional MEMS switches. In some embodiments, a MEMS switch may include a resilient contact element comprising a beam and a tip configured to wipe a contact surface; and a MEMS actuator having an open position that maintains the tip and the contact surface in a spaced apart relation and a closed position that brings the tip into contact with the contact surface, wherein the resilient contact element and the MEMS actuator are disposed on a substrate and are movable in a plane substantially parallel to the substrate. In some embodiments, various contact elements are provided for the MEMS switch. In some embodiments, various actuators are provided for control of the operation of the MEMS switch.

Abstract: Methods and apparatus for switching electrical signals are provided herein. In some embodiments a smart switch is provided, the smart switch may include a switch having a wipe capability; a monitor coupled to the switch for monitoring a performance characteristic thereof; and a controller configured to provide a stepped change in wipe applied by the switch between closing cycles thereof in response to the monitored performance characteristic. In some embodiments, an electronic device may be provided having a smart switch disposed therein.

Abstract: Embodiments of the present invention provide microelectromechanical systems (MEMS) switching methods and apparatus having improved performance and lifetime as compared to conventional MEMS switches. In some embodiments, a MEMS switch may include a resilient contact element comprising a beam and a tip configured to wipe a contact surface; and a MEMS actuator having an open position that maintains the tip and the contact surface in a spaced apart relation and a closed position that brings the tip into contact with the contact surface, wherein the resilient contact element and the MEMS actuator are disposed on a substrate and are movable in a plane substantially parallel to the substrate. In some embodiments, various contact elements are provided for the MEMS switch. In some embodiments, various actuators are provided for control of the operation of the MEMS switch.