Patents by Inventor Jaspreet Singh Gandhi

Jaspreet Singh Gandhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373989
    Abstract: A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 28, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 11355412
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 7, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 11315858
    Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Yu Hsiang Sun, Suresh Ramalingam, Tien-Yu Lee, Jaspreet Singh Gandhi
  • Patent number: 11302674
    Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 12, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, William E. Allaire, Hong Shi, Kerry M. Pierce
  • Patent number: 11282776
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch
  • Patent number: 11282775
    Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 22, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 11217550
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 4, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 11195780
    Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Suresh Ramalingam
  • Publication number: 20210366873
    Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Jaspreet Singh GANDHI, Suresh RAMALINGAM, William E. ALLAIRE, Hong SHI, Kerry M. PIERCE
  • Patent number: 11145566
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 12, 2021
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet Singh Gandhi, Cheang-Whang Chang
  • Patent number: 11127643
    Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 21, 2021
    Assignee: XILINX, INC.
    Inventors: Vadim Heyfitch, Jaspreet Singh Gandhi
  • Patent number: 11114360
    Abstract: Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the interposer are encapsulated with an encapsulant. The encapsulant is disposed in the second gap.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Myongseob Kim
  • Publication number: 20210249328
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Gamal REFAI-AHMED, Suresh RAMALINGAM, Jaspreet Singh GANDHI, Cheang-Whang CHANG
  • Publication number: 20210193620
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet Singh Gandhi, Cheang-Whang Chang
  • Publication number: 20210134757
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Jaspreet Singh GANDHI, Suresh RAMALINGAM
  • Patent number: 10971474
    Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu
  • Patent number: 10930611
    Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee
  • Patent number: 10879157
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 29, 2020
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20200303341
    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Xilinx, Inc.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Patent number: 10770430
    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 8, 2020
    Assignee: XILINX, INC.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi