Patents by Inventor Jaspreet Singh Gandhi

Jaspreet Singh Gandhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134757
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Jaspreet Singh GANDHI, Suresh RAMALINGAM
  • Patent number: 10971474
    Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu
  • Patent number: 10930611
    Abstract: An integrated circuit assembly having an improved solder connection, and methods for fabricating the same are provided that utilize platelets within the solder connections to inhibit solder connection failure, thus providing a more robust solder interface. In one example, an integrated circuit assembly is provided that includes a package substrate having a first plurality of contact pads exposed on a first surface of the package substrate and a second plurality of contact pads exposed on a second surface of the package substrate. The second plurality of contact pads have a pitch that is greater than a pitch of the first plurality of contact pads. Interconnect circuitry is disposed in the package substrate and couples the first and second pluralities of contact pads. At least a first contact pad of the second plurality of contact pads includes a solder ball disposed directly in contact with a palladium layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee
  • Patent number: 10879157
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 29, 2020
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20200303341
    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Xilinx, Inc.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Patent number: 10770430
    Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 8, 2020
    Assignee: XILINX, INC.
    Inventors: Myongseob Kim, Henley Liu, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Publication number: 20200161229
    Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Xilinx, Inc.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20200105642
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
  • Patent number: 10593638
    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 17, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, Henley Liu
  • Publication number: 20200035635
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam
  • Patent number: 10527670
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi
  • Patent number: 10529645
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 7, 2020
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10403591
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20190259695
    Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 22, 2019
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Vadim Heyfitch
  • Patent number: 10319606
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber, Suresh Ramalingam
  • Publication number: 20190131265
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: Xilinx, Inc.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10236229
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid. The packaging substrate has a die receiving area that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate. The lid a surface that includes a first region and a second region. The first region is disposed over the first IC die while the second region of the lid extends below the second surface the first IC die and is spaced above the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 19, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Publication number: 20180358280
    Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: Xilinx, Inc.
    Inventors: Jaspreet Singh Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10096502
    Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 9, 2018
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang, Jaspreet Singh Gandhi
  • Publication number: 20180284187
    Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, David M. Mahoney, Mohsen H. Mardi