Abstract: A method, includes: applying a read voltage at a first read voltage level to read a memory cell for detecting a resistance level of the memory cell; applying the read voltage at a second read voltage level, different from the first read voltage level, to read the memory cell for determining a waveform type has been utilized to program the memory cell; recognizing data bits stored in the memory cell. The data bits stored in the memory cell comprise a first data bit and at least one second data bit. The first data bit is recognized according to the waveform type and is irrelevant with the resistance level. The at least one second data bit is recognized according to the resistance level and is irrelevant with the waveform type. A device is also disclosed herein.

Abstract: In some embodiments, the present disclosure relates to a method of operating a phase change memory cell, which includes writing a first data state and a second data state to the phase change memory cell. To write the first data state, a phase change material (PCM) is heated to a melting point of the PCM, and then cooled to an ambient temperature below the melting point of the PCM over a first predetermined time period, thereby solidifying the PCM to correspond to the first data state. To write the second data state, the PCM is heated to the melting point of the PCM, and then cooled to the ambient temperature over a second predetermined cooling time period, thereby solidifying the PCM to correspond to the second data state. The second predetermined cooling time period differs from the first predetermined time period.

Abstract: A method is disclosed including following operations. A first signal is applied to memory cells in a memory device, to adjust resistance values of the memory cells. After the first signal is applied, a second signal is applied to the memory cells other than the first memory cell, to further adjust the resistance values of the plurality of memory cells other than the first memory cell. After the second signal is applied, data corresponding to the first predetermined resistance value and the second predetermined resistance value is stored in the first memory cell and the second memory cell, respectively. The first signal is configured for controlling a first memory cell in the memory cells to have a first predetermined resistance value. The second signal is configured for controlling a second memory cell in the memory cells to have a second predetermined resistance value.

Abstract: Methods for programming or reading a memory cell are disclosed. The methods include following operations. A read voltage at a first read voltage level is applied to read a memory cell for detecting a resistance level of the memory cell. The read voltage at a second read voltage level, different from the first read voltage level, is applied to read the memory cell for determining a waveform type has been utilized to program the memory cell. The resistance level and the waveform type are combined to recognize data bits stored in the memory cell.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: The present disclosure provides a phase change memory structure, including a bottom electrode, a first phase change material contacting a top surface of the bottom electrode, a first switch over the first phase change material, a second phase change material over the first switch, and a top electrode over the second phase change material.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate. A bottom electrode via opening is formed in the dielectric layer. A bottom electrode is formed in the bottom electrode via opening. The bottom electrode is etched back. A selector is formed in the bottom electrode via opening and over the bottom electrode. A memory layer is formed over the selector. A top electrode is formed over the memory layer.

Abstract: A key structure includes a movable support element, a keycap, and a fitting portion. The keycap includes a top surface, a bottom surface, and a rim, the bottom surface is jointed with the movable support element, and a periphery of the top surface extends downward to form the rim. The fitting portion is located on the rim, and operated by an operation body to separate the keycap from the movable support element.

Abstract: The present disclosure provides a phase change memory structure, including a bottom electrode, a first phase change material contacting a top surface of the bottom electrode, a first switch over the first phase change material, a second phase change material over the first switch, and a top electrode over the second phase change material.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage layer. A top electrode overlies a bottom electrode. The data storage layer is disposed between the top and bottom electrodes. The data storage layer has a first region and a second region. The first region comprises a first material and the second region comprises a compound of the first material and a reactive species.

Abstract: A method is disclosed including following operations. A first signal is applied to memory cells in a memory device, to adjust resistance values of the memory cells. After the first signal is applied, a second signal is applied to the memory cells other than the first memory cell, to further adjust the resistance values of the plurality of memory cells other than the first memory cell. After the second signal is applied, data corresponding to the first predetermined resistance value and the second predetermined resistance value is stored in the first memory cell and the second memory cell, respectively. The first signal is configured for controlling a first memory cell in the memory cells to have a first predetermined resistance value. The second signal is configured for controlling a second memory cell in the memory cells to have a second predetermined resistance value.

Abstract: A method includes forming a dielectric layer over a conductive layer, and forming a sidewall spacer in an opening in the dielectric layer. The opening exposes a portion of the conductive layer. A bottom electrode layer is formed over the conductive layer and the sidewall spacer. A phase change material layer is formed over the bottom electrode layer, and a top electrode layer is formed over the phase change material layer. In an embodiment, the method includes recess etching the bottom electrode layer before forming the phase change material layer.

Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.

Abstract: Methods for programming or reading a memory cell are disclosed. The methods include following operations. A read voltage at a first read voltage level is applied to read a memory cell for detecting a resistance level of the memory cell. The read voltage at a second read voltage level, different from the first read voltage level, is applied to read the memory cell for determining a waveform type has been utilized to program the memory cell. The resistance level and the waveform type are combined to recognize data bits stored in the memory cell.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: The current disclosure describes techniques for patterning a phase-change memory layer. A SiON layer is used as a first hard mask and an electrical conductive protective layer is used as a second hard mask to pattern the phase-change memory layer. An organic BARC layer is sued to improve the photolithography accuracy. The thickness ratio between the organic BARC layer and the hard mask SiON layer and the etching conditions of the hard mask SiON layer are controlled such that the patterned organic BARC layer is completely or near completely resolved simultaneously with the patterning of the hard mask SiON layer.

Abstract: A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.

Abstract: A method for forming a phase change random access memory (PCRAM) device is provided. The method includes: forming a memory stack over an insulator layer. A first etch process is performed to pattern the memory stack defining a memory cell including a top electrode overlying a dielectric layer. The dielectric layer includes a center region laterally between a first outer region and a second outer region. An etchant used in the first etch process creates a compound in the first and second outer regions, the compound has a first melting point temperature. A first deposition process is performed to form a first sidewall spacer over the memory cell, the first sidewall spacer is in direct contact with outer sidewalls of the memory cell. The first deposition process reaches a first maximum temperature less than the first melting point temperature.

Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

Abstract: The present disclosure provides a phase change memory structure, including a bottom electrode, a first phase change material contacting a top surface of the bottom electrode, a first switch over the first phase change material, a second phase change material over the first switch, and a top electrode over the second phase change material.