Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

Abstract: In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Abstract: A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: According to some embodiments, a plurality of ring oscillators are associated with a generation and/or distribution of a clock signal.

Abstract: According to some embodiments, a clock signal having an adaptive frequency is provided.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: According to some embodiments, a clock signal having an adaptive frequency is provided.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is located at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated by the phase locked loops. A plurality of phase shifted, tester generated clock signals may be subjected to an exclusive OR operation for generating input/output and core clock replacement signals. The clock signals received from the tester may also be aligned. Thus, a variety of skews may be compensated before entering the bypass mode. In some embodiments of the present invention, the core and I/O PLL clocks are used to establish alignment in a set-up phase and in other embodiments, the core and I/O PLL need not be utilized at all to generate appropriate internal clock signals from an external tester.

Abstract: According to some embodiments, a plurality of ring oscillators are associated with a generation and/or distribution of a clock signal.