Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.

Abstract: A logic circuit is disclosed having a digital divider that is capable of generating an intermediate signal in response to an input digital clock signal having a 50% duty cycle, where the intermediate signal has a non-50% duty cycle. First and second output signals are generated by a digital delay circuit in response to the intermediate signal. In the digital delay circuit, the first output signal is delayed by an odd number of substantially identical inverter delays, while the second output signal is delayed by an even number of inverter delays. Such a circuit helps reduce and perhaps minimize the sensitivity of the relative phase difference between the output signals to variations in temperature, supply voltage, and fabrication process parameters.

Abstract: A hierarchical power control system for an integrated circuit may be integrated into a clocking system that includes a global clock generator, a clock distribution network in communication with the global clock generator and a plurality of functional unit blocks each in communication with the global clock generator. The hierarchical power control system may include a first power controller provided in a communication path between the global clock generator and the clock distribution network, and a plurality of second power controllers, one provided in each communication path between the clock distribution network and a functional unit block.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is provided at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock signal is corrected based on the results of this comparison with the reference clock signal. The clock signal may be corrected by using a programmable delay compensator. A second clock signal at a second location in the processor may be compared with the corrected first clock signal and the second clock signal may be corrected based on the results of the comparison. The compensators may be permanently programmed as required using fuses associated with compensator control bits.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.