Patents by Inventor Javier Carretero Casado
Javier Carretero Casado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10528473Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: June 13, 2017Date of Patent: January 7, 2020Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
-
Patent number: 10020037Abstract: An apparatus for storing X-bit digitized data, the register file comprising: a plurality of registers each register configured for storing X bits, wherein each register is partitioned into Y sub-registers such that each sub-register stores at least X/Y bits, and wherein at least one extra X/Y-bit sub-register is incorporated in each register to provide redundancy in the number of sub-registers for a total of at least Y+1 sub-registers per register, so that if a first sub-register in a first register includes faulty bits, data destined for storage in the first sub-register is stored in a second sub-register, in the first register, that does not include faulty bits.Type: GrantFiled: December 10, 2007Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera
-
Patent number: 9940686Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: GrantFiled: May 14, 2014Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Patent number: 9922393Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: GrantFiled: October 8, 2015Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Publication number: 20180060239Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: ApplicationFiled: June 13, 2017Publication date: March 1, 2018Inventors: CHRISTOPHER WILKERSON, MUHAMMAD M. KHELLAH, VIVEK DE, MING ZHANG, JAUME ABELLA, JAVIER CARRETERO CASADO, PEDRO CHAPARRO MONFERRER, XAVIER VERA, ANTONIO GONZALEZ
-
Patent number: 9904977Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: GrantFiled: July 18, 2016Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Publication number: 20170201459Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: MATTEO MONCHIERO, JAVIER CARRETERO CASADO, ENRIC HERRERO ABELLANAS, TANAUSU RAMIREZ, XAVIER VERA
-
Patent number: 9678878Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.Type: GrantFiled: October 16, 2012Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
-
Patent number: 9608922Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.Type: GrantFiled: December 23, 2011Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Matteo Monchiero, Javier Carretero Casado, Enric Herrero Abellanas, Tanausu Ramirez, Xavier Vera
-
Publication number: 20160342495Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: XAVIER VERA, JAVIER CARRETERO CASADO, MATTEO MONCHIERO, TANAUSU RAMIREZ, ENRIC HERRERO ABELLANAS
-
Publication number: 20160328820Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Patent number: 9405647Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.Type: GrantFiled: December 30, 2011Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Xavier Vera, Javier Carretero Casado, Matteo Monchiero, Tanausu Ramirez, Enric Herrero
-
Patent number: 9374542Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.Type: GrantFiled: March 28, 2014Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Kyriakos Stavrou, Pedro Marcuello, Grigorios Magklis, Javier Carretero Casado, Juan Fernandez, Carlos Madriles, Daniel Ortega, Demos Pavlou
-
Patent number: 9286172Abstract: Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.Type: GrantFiled: December 22, 2011Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Tanausu Ramirez, Javier Carretero Casado, Enric Herrero, Matteo Monchiero, Xavier Vera
-
Publication number: 20160027144Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: ApplicationFiled: October 8, 2015Publication date: January 28, 2016Inventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Publication number: 20150332429Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.Type: ApplicationFiled: May 14, 2014Publication date: November 19, 2015Inventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
-
Patent number: 9176895Abstract: A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.Type: GrantFiled: March 16, 2013Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Xavier Vera, Javier Carretero Casado, Enric Herrero Abellanas, Daniel Sanchez, Nicholas Axelos, Tanausu Ramirez
-
Patent number: 9170947Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.Type: GrantFiled: December 29, 2011Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Xavier Vera, Matteo Monchiero, Javier Carretero Casado, Enric Herrero, Tanausu Ramirez
-
Publication number: 20150281602Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: KYRIAKOS STAVROU, PEDRO MARCUELLO, GRIGORIOS MAGKLIS, JAVIER CARRETERO CASADO, JUAN FERNANDEZ, CARLOS MADRILES, DANIEL ORTEGA, DEMOS PAVLOU
-
Patent number: 9112537Abstract: Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.Type: GrantFiled: December 22, 2011Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Tanausu Ramirez, Javier Carretero Casado, Enric Herrero, Matteo Monchiero, Xavier Vera