Patents by Inventor Javier Soto

Javier Soto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953434
    Abstract: Disclosed is a spectroscopic device, system, and method for measuring the concentration of one or more molecular species of interest in a gas, liquid or solid sample, where the device may be portable, may be commercially manufactured, and/or may be adapted to existing systems and/or integrated with new systems to provide optical gas sensing for such systems. The disclosed devices, systems, and methods can be particularly useful in monitoring the purity of, e.g., a certain gas species, including determining whether a gas mixture contains certain gas species above a set concentration limit.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 9, 2024
    Assignees: SHELL OIL COMPNY, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Mark Zondlo, Lei Tao, Da Pan, Josh Collins, Paul Guiguizian, Howard Y. Bell, Alice Margaret Sophie Elliott, Patrick Minter Killough, Bernardus Maria Geertshuis, Herie Javier Soto
  • Patent number: 11898956
    Abstract: Disclosed is a spectroscopic device, system, and method for measuring the concentration of one or more molecular species of interest in a gas, liquid or solid sample, where the device may be portable, may be commercially manufactured, and/or may be adapted to existing systems and/or integrated with new systems to provide optical gas sensing for such systems. The disclosed devices, systems, and methods can be particularly useful in monitoring the purity of, e.g., a certain gas species, including determining whether a gas mixture contains certain gas species above a set concentration limit.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 13, 2024
    Assignees: SHELL OIL COMPNY, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Mark Zondlo, Lei Tao, Da Pan, Josh Collins, Paul Guiguizian, Howard Y. Bell, Alice Margaret Sophie Elliott, Patrick Minter Killough, Bernardus Maria Geertshuis, Herie Javier Soto
  • Patent number: 11881457
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Patent number: 11791528
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20230326866
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 12, 2023
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Patent number: 11735531
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Patent number: 11532584
    Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
  • Publication number: 20220231394
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
  • Publication number: 20220187203
    Abstract: Disclosed is a spectroscopic device, system, and method for measuring the concentration of one or more molecular species of interest in a gas, liquid or solid sample, where the device may be portable, may be commercially manufactured, and/or may be adapted to existing systems and/or integrated with new systems to provide optical gas sensing for such systems. The disclosed devices, systems, and methods can be particularly useful in monitoring the purity of, e.g., a certain gas species, including determining whether a gas mixture contains certain gas species above a set concentration limit.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 16, 2022
    Applicant: The Trustees of Princeton University
    Inventors: Mark ZONDLO, Lei TAO, Da PAN, Josh COLLINS, Howard Y. Bell, Alice Margaret Sophie ELLIOTT, Patrick Minter KILLOUGH, Bernardus Maria GEERTSHUIS, Herie Javier SOTO
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20220102261
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 31, 2022
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
  • Patent number: 11227825
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
  • Publication number: 20210343653
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Patent number: 11107766
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • Patent number: 11101222
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta, Javier Soto Gonzalez, Kwangmo Lim
  • Publication number: 20210225807
    Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Javier SOTO GONZALEZ, Shawna M. LIFF
  • Publication number: 20210193583
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Adel A. ELSHERBINI, Johanna M. SWAN, Shawna M. LIFF, Henning BRAUNISCH, Krishna BHARATH, Javier SOTO GONZALEZ, Javier A. FALCON
  • Patent number: 11004824
    Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Javier Soto Gonzalez, Shawna M. Liff
  • Patent number: 10978399
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Sai Boyapati, Wei-Lun Kane Jen, Javier Soto Gonzalez
  • Patent number: 10971416
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao