Patents by Inventor Javier Soto
Javier Soto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971453Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: GrantFiled: September 30, 2016Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Publication number: 20210066232Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.Type: ApplicationFiled: November 16, 2020Publication date: March 4, 2021Applicant: Intel CorporationInventors: Robert Alan May, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
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Publication number: 20210035818Abstract: Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Tarek A. IBRAHIM, Rahul N. MANEPALLI, Wei-Lun K. JEN, Steve S. CHO, Jason M. GAMBA, Javier SOTO GONZALEZ
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Patent number: 10898798Abstract: An air flow generator may be implemented on an augmented reality (AR) or virtual reality (VR) controller or head-mounted display (HMD) through which an AR or VR experience is presented. Based on content upon which the AR or VR experience is based, air flow effects can be provided by the air flow generator. In particular, desired air flow effect parameters based on or obtained from the content, can be used to enhance the AR or VR experience through generating air flow directed at a user of the HMD. The air flow generated by the air flow generator can be further enhanced by the addition of liquid and/or scented additives.Type: GrantFiled: December 26, 2017Date of Patent: January 26, 2021Assignee: DISNEY ENTERPRISES, INC.Inventors: Steven M. Chapman, Javier Soto, Mehul Patel, Joseph Popp, Calis Agyemang
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Patent number: 10872872Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.Type: GrantFiled: December 30, 2016Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Robert Alan May, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
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Patent number: 10798817Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: GrantFiled: December 11, 2015Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Aleksandar Aleksov, Javier Soto Gonzalez, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne
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Publication number: 20200235449Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: ApplicationFiled: April 6, 2020Publication date: July 23, 2020Inventors: Adel A. ELSHERBINI, Mathew MANUSHAROW, Krishna BHARATH, Zhichao ZHANG, Yidnekachew S. MEKONNEN, Aleksandar ALEKSOV, Henning BRAUNISCH, Feras EID, Javier SOTO
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Patent number: 10651525Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: June 4, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
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Publication number: 20200051915Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.Type: ApplicationFiled: March 31, 2017Publication date: February 13, 2020Inventors: Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Sai Boyapati, Wei-Lun Kane Jen, Javier Soto Gonzalez
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Publication number: 20200020636Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.Type: ApplicationFiled: September 18, 2019Publication date: January 16, 2020Inventors: Javier Soto GONZALEZ, Houssam JOMAA
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Publication number: 20190363063Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.Type: ApplicationFiled: December 30, 2016Publication date: November 28, 2019Applicant: Intel CorporationInventors: Robert Alan MAY, Sri Ranga Sai Boyapati, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim, Aleksandar Aleksov
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Publication number: 20190355636Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
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Patent number: 10461032Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.Type: GrantFiled: February 1, 2013Date of Patent: October 29, 2019Assignee: Intel CorporationInventors: Javier Soto Gonzalez, Houssam Jomaa
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Patent number: 10410939Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.Type: GrantFiled: December 16, 2015Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
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Publication number: 20190259705Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: ApplicationFiled: September 30, 2016Publication date: August 22, 2019Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Patent number: 10381291Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.Type: GrantFiled: September 25, 2015Date of Patent: August 13, 2019Assignee: Intel CorporationInventors: Adel A. Elsherbini, Henning Braunisch, Brandon M. Rawlings, Aleksandar Aleksov, Feras Eid, Javier Soto
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Publication number: 20190192965Abstract: An air flow generator may be implemented on an augmented reality (AR) or virtual reality (VR) controller or head-mounted display (HMD) through which an AR or VR experience is presented. Based on content upon which the AR or VR experience is based, air flow effects can be provided by the air flow generator. In particular, desired air flow effect parameters based on or obtained from the content, can be used to enhance the AR or VR experience through generating air flow directed at a user of the HMD. The air flow generated by the air flow generator can be further enhanced by the addition of liquid and/or scented additives.Type: ApplicationFiled: December 26, 2017Publication date: June 27, 2019Applicant: Disney Enterprises, Inc.Inventors: STEVEN M. CHAPMAN, JAVIER SOTO, MEHUL PATEL, JOSEPH POPP, CALIS AGYEMANG
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Publication number: 20190189563Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.Type: ApplicationFiled: September 29, 2016Publication date: June 20, 2019Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
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Patent number: 10327330Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.Type: GrantFiled: September 24, 2015Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Javier Soto Gonzalez, Dilan Seneviratne, Shruti R. Jaywant, Sashi S. Kandanur, Srinivas Pietambaram, Nadine L. Dabby, Braxton Lathrop, Rajat Goyal, Vivek Raghunathan
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Patent number: 10204855Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.Type: GrantFiled: July 11, 2014Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Alejandro Levander, Tatyana Andryushchenko, David Staines, Mauro Kobrinsky, Aleksandar Aleksov, Dilan Seneviratne, Javier Soto Gonzalez, Srinivas Pietambaram, Rafiqul Islam