Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

Abstract: A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.

Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to the first AC component signal and the second AC component signal.

Abstract: One aspect of this description relates to a convolutional neural network (CNN). The CNN includes a memory cell array including a plurality of memory cells. Each memory cell includes at least one first capacitive element of a plurality of first capacitive elements. Each memory cell is configured to multiply a weight bit and an input bit to generate a product. The at least one first capacitive element is enabled when the product satisfies a predetermined threshold. The CNN includes a reference cell array including a plurality of second capacitive elements. The CNN includes a memory controller configured to compare a first signal associated with the plurality of first capacitive elements with a second signal associated with at least one second capacitive element of the plurality of second capacitive elements, and, based on the comparison, determine whether the at least one first capacitive element is enabled.

Abstract: Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.

Abstract: Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.

Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.

Abstract: A device is disclosed. The device includes an operational amplifier, an output circuit and a first feedback circuit. The operational amplifier includes an input terminal that is configured to receive a feedback signal. The output circuit is coupled to an output terminal of the operational amplifier and is configured to generate an output signal in response to an output of the operational amplifier. The first feedback circuit is coupled to the output circuit and is configured to couple at least one first ripple signal in the output signal to the input terminal of the operational amplifier that is configured to receive the feedback signal, for adjusting the output signal. A method also is disclosed herein.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, a first switch, and a second switch. The first differential input pair receives an output voltage at an output node and a first temperature-dependent voltage. The second differential input pair receives the output voltage and a second temperature-dependent voltage. When the output voltage reaches the second temperature-dependent voltage, the first switch is turned on to pull up the output voltage in response to a first control signal generated according to an output signal of the second differential input pair. When the output voltage reaches the first temperature-dependent voltage, the second switch is turned on to pull down the output voltage in response to a second control signal generated according to an output signal of the first differential input pair.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: A computing device and method are provided. The computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-period lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the levels of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charge or discharge the conductive line to a voltage indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum.

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A circuit is disclosed that includes a capacitive element, a control circuit, and a first switch and a second switch. The capacitive element is configured to generate an output voltage at a terminal thereof. The control circuit is configured to generate a first control signal and a second control signal in response to a first temperature-dependent voltage, a second temperature-dependent voltage, and the output voltage. The first switch and the second switch are coupled to the capacitive element, and configured to be turned on or off in response to the first control signal and the second control signal respectively. The first switch and the second switch have different switching status from each other in a charge mode.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.