Abstract: A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.

Abstract: A method of forming a semiconductor device includes implanting dopants in a first region of the semiconductor device to form a source region. The method further includes forming a guard ring in a second region of the semiconductor device, the guard ring being separated from the source region by a first spacing. The method further includes depositing a first heat conductive layer over the source region, wherein the first heat conductive layer is directly coupled to the source region and directly coupled to the guard ring. The first heat conductive layer is configured to dissipate heat generated by the semiconductor device from the source region to the guard ring.

Abstract: A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry.

Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.

Abstract: In some embodiments, a semiconductor device includes a cell array, a first region and a second region. The first region surrounds the cell array and has a first pattern density. The second region is between the cell array and the first region. The second region surrounds the cell array and has a second pattern density smaller than a third pattern density of the cell array, which in turn is smaller than the first pattern density.

Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.

Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.

Abstract: A circuit is disclosed that includes a first differential input pair and a second differential input pair. The first differential input pair is activated according to an output of the second differential input pair, and receives a first temperature-dependent voltage and an output signal. The second differential input pair is activated according to an output of the first differential input pair, and receives a second temperature-dependent voltage and the output signal. The switching circuit couples a capacitive element to a first voltage supply according to the output of the first differential input pair, and the capacitive element to a second voltage supply according to the output of the second differential input pair, to generate the output signal.

Abstract: In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.

Abstract: In some embodiments, a semiconductor device includes a cell array, a first region and a second region. The first region surrounds the cell array and has a first pattern density. The second region is between the cell array and the first region. The second region surrounds the cell array and has a second pattern density smaller than a third pattern density of the cell array, which in turn is smaller than the first pattern density.

Abstract: A temperature sensor arrangement in an integrated circuit (IC) includes a sensor array configured to determine a temperature of the IC. The sensor array includes a first transistor having a first terminal, a second terminal and a gate. The temperature sensor array further includes a guard ring region between the sensor array and another circuit of the IC. The guard ring region includes a transistor structure having a first terminal, a second terminal and a gate. The temperature sensor arrangement further includes a thermally conductive element connected to the transistor structure and a first terminal of the first transistor. The thermally conductive element is configured to provide a thermally conductive path from the transistor structure to the first terminal of the first transistor.

Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K<N. The first transistors have the same channel length, and the second transistors have the same channel length.

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

Abstract: An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array.

Abstract: A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.

Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.

Abstract: Some embodiments of the present disclosure provide a method including turning on a noise-measuring system for a device under test (DUT) with the DUT turned off; measuring a first phase noise caused by the noise-measuring system; turning on the DUT; measuring a second phase noise caused by the noise-measuring system and the DUT; and subtracting the first phase noise from the second phase noise to obtain a third phase noise caused by the DUT.

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Abstract: A device includes a bandgap reference stage, a mirror current source, a voltage control circuit, and a resistive device. The mirror current source has a control terminal electrically coupled to an internal node of the bandgap reference stage. The voltage control circuit includes a first terminal electrically coupled to a second internal node of the bandgap reference stage, and a second terminal electrically coupled to a first terminal of the mirror current source. The resistive device has a first terminal electrically coupled to a third terminal of the voltage control circuit.