Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.

Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.

Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract: The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid.

Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.