Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: A method for electron-beam writing to a medium includes positioning the medium within an e-beam writing machine so that the medium is supported by a stage and is exposed to an e-beam source. The method also includes writing a pattern to the medium using a plurality of independently-controllable beams of the e-beam source, in which the pattern comprises a plurality of parallel strips. Each of the parallel strips is written using multiple ones of the independently-controllable beams.

Abstract: A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

Abstract: Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.

Abstract: A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

Abstract: Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.

Abstract: Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.

Abstract: A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

Abstract: A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

Abstract: A method and associated masks for carrying out a lithographic imaging process to reduce or avoid a strong interference effect in off-axis illumination, the method including providing a resist layer on a substrate; illuminating a first group of line patterns through a first mask on the resist layer; illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and, developing the illuminated resist layer.

Abstract: Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.

Abstract: Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.

Abstract: An alignment mark configuration, wherein the alignment mark is protected from being damaged from the subsequent planarization process, is described. The alignment mark configuration comprises a plurality of recesses and a flat spacing between the recesses on the substrate. If the substrate further comprises a trench structure, the spacing between the trench structure and the alignment mark is at least 5 times the flat spacing between the neighboring recesses of the alignment mark.

Abstract: A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

Abstract: A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

Abstract: A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

Abstract: Prior art methods for forming alt. PSMs require a relatively large number of phase assignments to avoid phase conflicts in complex arrays. This has been improved by adding dummy elements at the ends of all rows and columns of the array that is to be imaged, while initially leaving all corners open. Phases are then assigned in checker board fashion to all elements. Additional dummy elements are then placed in the open corners and assigned the same phase as their immediate neighbors. The first exposure of the photoresist is made with both the original elements and the additional dummy elements. Then additional resist is coated and exposed and the original elements are open after development. If the added elements are made somewhat smaller than the original elements, only a single exposure is used.

Abstract: Secondary mask pattern elements are used to interconnect isolated sub-patterns of a mask pattern. The interconnection of the isolated sub-patterns prevents different electrostatic charge accumulation on the various isolated sub-patterns. This prevents mask damage due to electrostatic discharge, problems with mask inspection, and problems with mask repair due to different electrostatic charge accumulation on various isolated sub-patterns. The mask is used to transfer the mask pattern to a layer of photosensitive material. The width of the secondary sub-pattern elements are sufficiently small relative to the wavelength of the light used to transfer the mask pattern to the photosensitive material that the secondary sub-pattern elements are not transferred to the photosensitive material.