Abstract: Techniques for offloading operations to access data that is compressed and distributed to multiple storage nodes are disclosed. A storage node includes one or more storage devices to store a portion of compressed data. Other portions of the compressed data are stored on other storage nodes. A storage node receives a request to perform an operation on the data, decompresses at least part of the portion of the locally stored compressed data, and performs the operation on the decompressed part, returning the operation result to a compute node. Any part that could not be decompressed can be sent with the request to the next storage node. The process continues until all the storage nodes storing the compressed data receive the request, decompress the locally stored data, and perform the operation on the decompressed data.

Abstract: Apparatuses, systems, and methods having positionally aware communication between a controller and a plurality of solid state drives (SSD) over a multi-wire serial bus is described. An example electronic device includes a multi-wire serial bus, multiple SSD connectors coupled to the multi-wire serial bus, and a serial bus position address (BPos) line to uniquely identify the physical position of each SSD connector with a unique BPos identifier (ID). The device also includes a serial bus controller coupled to the multi-wire serial bus and further comprising circuitry configured to communicate with a specific SSD connector at a known physical position by associating the BPos ID of the specific SSD connector with the communication.

Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.

Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.

Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.

Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.

Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that digitally signs a hash table and a data payload, wherein the data payload is partitioned into a plurality of storage blocks and the hash table specifies how to index into and individually authenticate the plurality of storage blocks. Additionally, a write of the digitally signed hash table and data payload may be initiated to an aggregate storage array. In one example, the aggregate storage array authenticates the digital signature of the hash table and the data payload and conducts a write of the data payload to a plurality of drives in the aggregate storage array in accordance with the hash table.

Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

Abstract: A device transmits the capabilities of the device for performing transformations on offloaded objects, to a host. The device receives an object definition command from the host, where the object definition command indicates one or more transformations to apply to an object. One or more transformations are performed on the object to generate one or more transformed objects. A completion command is transmitted to the host to indicate completion of the one or more transformations on the object.

Abstract: Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity further includes a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB.

Abstract: One embodiment provides a storage device. The storage device includes a storage I/O (input/output) logic and a storage device controller. The storage I/O logic is to couple the storage device to a host device, the storage I/O logic to receive a sort-merge command the host device. The a storage device controller is to identify a level N SSTable (sorted string table) file, a corresponding level N index file, a first level N+1 SSTable file and a corresponding first level N+1 index file, in response to the sort-merge command to be received from the host device. The storage device controller is further to perform a sort-merge of the level N SSTable file and the first level N+1 SSTable file to produce a first level N+1 output SSTable file and a first level N+1 output SSTable index file. The level N SSTable file includes at least one level N key-value (KV) pair. The level N+1 SSTable file includes at least one level N+1 key-value (KV) pair.

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

Abstract: Technologies for providing error correction for row direction and column direction in a cross point memory include a memory that includes media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is configured to read, from the memory media, a column of data. Additionally, the media access circuitry is configured to read, from the memory media, column error correction code (ECC) check data appended to the column of data and perform error correction on the column of data with the column ECC check data to produce error-corrected data.

Abstract: Technologies for performing in-memory training data augmentation for artificial intelligence include a memory comprising media access circuitry connected to a memory media. The media access circuitry is to obtain an input training data set that includes an initial amount of data samples that are usable to train a neural network. The media access circuitry is further to produce, from the input training data set, an augmented training data set with more data samples than the input training data set.