Patents by Inventor Jawad Khan
Jawad Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11829376Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.Type: GrantFiled: May 6, 2020Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Mariano Tepper, Dipanjan Sengupta, Jawad Khan, Sourabh Dongaonkar, Chetan Chauhan, Richard Coulson, Theodore Willke
-
Patent number: 11789641Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: GrantFiled: June 16, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
-
Publication number: 20230305709Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.Type: ApplicationFiled: September 15, 2020Publication date: September 28, 2023Inventors: Dipanjan Sengupta, Mariano Tepper, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson
-
Publication number: 20230222417Abstract: A software system comprising of many-to-many input data sources, data, storage and processing medium, executable software instructions that, when executed by the application, enable the software to receive, standardize heterogenous data, and perform business translation logic. This data translation and standardization process generates a standard object hierarchy, organizing outcome in common translatable objects corresponding to active graphical user interface elements. The application enables interface of heterogenous datasets with a hierarchical representation of the data as active GUI elements, creating an interfacing object for each of the active GUI elements represented in the hierarchical representation; and organizing the objects into the standard hierarchy based on relationships among active GUI elements.Type: ApplicationFiled: January 9, 2023Publication date: July 13, 2023Inventors: Jawad Khan, Ahmed Samnan Raza
-
Patent number: 11604834Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.Type: GrantFiled: May 8, 2020Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Mariano Tepper, Dipanjan Sengupta, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson, Rajesh Sundaram
-
Patent number: 11573735Abstract: Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.Type: GrantFiled: April 21, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Rowel Garcia, Jawad Khan, Richard Mangold
-
Publication number: 20230027351Abstract: Systems, apparatuses and methods may provide for technology that includes a single server to store a portion of a temporal graph to a first memory of the single server, and store a second portion of the temporal graph to a second memory of the single server, wherein an access rate of the first memory is greater than an access rate of the second memory, and wherein a capacity of the second memory is greater than a capacity of the first memory. The single server may also retrieve vertices of the second portion in response to a selectivity of an input query exceeding a cost model threshold.Type: ApplicationFiled: September 21, 2022Publication date: January 26, 2023Inventors: Joana Matos Fonseca da Trindade, Jawad Khan, Sanjeev Trika
-
Publication number: 20220405005Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Applicant: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
-
Patent number: 11526279Abstract: Technologies for scrambling functions in a column-addressable memory architecture includes a device having a memory and a circuitry. The memory includes a matrix storing individually addressable bit data, and the matrix is formed by rows and columns. The circuitry is to receive a request to perform a write operation of one or more bit values to one of the columns. The circuitry is further to determine a scrambler state at each location of the column, the location corresponding to a respective row and column index. The scrambler state is indicative of a function used to determine a value at the respective column location. Each of the bit values is scrambled as a function of the scrambler state for the respective column location and written thereto.Type: GrantFiled: May 12, 2020Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Zion Kwok, Jawad Khan, Richard Coulson
-
Publication number: 20220350525Abstract: An example of an apparatus may include memory organized as at least one bank that includes two or more arrays, and circuitry communicatively coupled to the memory to select respective rows of the two or more arrays of a bank for a memory access operation based on an access orientation signal. Other examples are disclosed and claimed.Type: ApplicationFiled: July 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Sourabh Dongaonkar, Shigeki Tomishima, Jawad Khan
-
Patent number: 11392494Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.Type: GrantFiled: June 5, 2020Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Jawad Khan, Chetan Chauhan, Rajesh Sundaram, Sourabh Dongaonkar, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper
-
Publication number: 20220188228Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a two level memory controller mode that uses a dynamic random access memory as a transparent cache for a persistent memory. For example, a memory controller includes logic to map cached data in the dynamic random access memory to an original address of copied data in the persistent memory. The cached data in the dynamic random access memory is tracked as to whether it is dirty data or clean data with respect to the copied data in the persistent memory. Upon eviction of the cached data from the dynamic random access memory, a writeback of the cached data that has been evicted to the persistent memory is bypassed when the cached data is tracked as dirty data.Type: ApplicationFiled: December 22, 2021Publication date: June 16, 2022Applicant: Intel CorporationInventors: Sanjeev Trika, Mark Hildebrand, Jawad Khan
-
Patent number: 11327881Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.Type: GrantFiled: May 13, 2020Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Chetan Chauhan, Sourabh Dongaonkar, Rajesh Sundaram, Jawad Khan, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper
-
Patent number: 11258539Abstract: Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.Type: GrantFiled: May 6, 2020Date of Patent: February 22, 2022Assignee: Intel CorporationInventors: Wei Wu, Sourabh Dongaonkar, Jawad Khan
-
Patent number: 11210195Abstract: An embodiment of a semiconductor apparatus may include technology to receive a request for storage-related resources, and demand-query one or more persistent storage media devices for device-determined performance-related information in response to the request, where the device-determined performance-related information is based on dynamically measured performance of persistent storage media of the device itself. Other embodiments are disclosed and claimed.Type: GrantFiled: August 14, 2018Date of Patent: December 28, 2021Assignee: Intel CorporationInventors: Jason Casmira, Jawad Khan, David Minturn
-
Publication number: 20210286549Abstract: Systems, apparatuses and methods may provide for technology that organizes data and corresponding parity information into a plurality of die words, distributes a column of the die words across a plurality of storage dies, and distributes the column across a plurality of partitions. In one example, the technology also reads a row of the die words at a read rate and reads the column of the die words at the read rate.Type: ApplicationFiled: May 21, 2021Publication date: September 16, 2021Inventors: Sourabh Dongaonkar, Jawad Khan
-
Patent number: 11074004Abstract: An embodiment of a semiconductor apparatus may include technology to segregate a persistent storage media into two or more segments, and collect telemetry information on a per segment-basis, wherein a segment granularity is smaller than a namespace granularity. Other embodiments are disclosed and claimed.Type: GrantFiled: January 15, 2019Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: Jason Casmira, Jawad Khan, David Minturn
-
Patent number: 10908825Abstract: An embodiment of a semiconductor apparatus may include technology to determine a persistent region and a non-persistent region of a volatile media based on an amount of power available from one or more backup power sources, and periodically backup only the non-persistent region of the volatile media to a non-volatile media. Other embodiments are disclosed and claimed.Type: GrantFiled: March 29, 2018Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Peng Li, Sanjeev Trika, Jawad Khan, Myron Loewen
-
Patent number: 10891233Abstract: Systems, apparatuses and methods may provide for technology to automatically identify a plurality of non-volatile memory locations associated with a file in response to a close operation with respect to the file and automatically conduct a prefetch from one or more of the plurality of non-volatile memory locations that have been most recently accessed and do not reference cached file segments. The prefetch may be conducted in response to an open operation with respect to the file and on a per-file segment basis.Type: GrantFiled: June 28, 2018Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Scott Burridge, William Chiu, Jawad Khan, Sanjeev Trika
-
Patent number: 10884916Abstract: An embodiment of a mass storage apparatus may include first non-volatile media, second non-volatile media which provides a relatively larger write granularity as compared to the first non-volatile media, and logic communicatively coupled to the first and second non-volatile media to direct an access request to one of the first non-volatile media and the second non-volatile media based on an indication from an operating system. An embodiment of a host computing apparatus may include a processor, memory communicatively coupled to the processor, and logic communicatively coupled to the processor to provide an indication for a file system-related access request to a mass storage device based on a granularity size for the file system-related access request. Other embodiments are disclosed and claimed.Type: GrantFiled: March 29, 2018Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Sanjeev Trika, Jawad Khan, Peng Li, Myron Loewen