Patents by Inventor Jay Chang

Jay Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130193755
    Abstract: A novel circuit scheme and control includes a plurality of identical DC-DC converters with an optimal modulation/harmonic controller and a load balancing portion or process in an integral and systematic design methodology. The modulation/harmonic controller can be configured to control the individual modules in an optimal and coordinated way in the time domain so as to substantially reduce or eliminate a large amount of high-frequency input current harmonics, thus reducing EMI, weight, and size and increasing redundancy. The load balancing portion or process can balance the loads on the converters in real time or offline.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: Eaton Corporation
    Inventors: Jie Jay Chang, Bhuvan Govindasamy
  • Publication number: 20130049608
    Abstract: A system for adaptively controlling and adjusting the output and balance of multiple integrated illuminated panels may include a plurality of illumination sources in operative connection with a plurality of integrated illuminated panels, the plurality of illumination sources being disposed within a vehicle cockpit. The system may also include a dimming control configured to provide manual adjustment of brightness of the plurality of illumination sources, and a digital controller configured to automatically harmonize chromaticity and brightness of the plurality of illumination sources based on detected ambient lighting conditions.
    Type: Application
    Filed: November 24, 2010
    Publication date: February 28, 2013
    Applicant: Eaton Corporation
    Inventors: Vanacan Tatavoosian, Jie Jay Chang
  • Publication number: 20120223974
    Abstract: The system includes a digital system architecture including digital chromaticity control. Such control may include color balance, luminance, and color compensation and/or harmonization of multiple integrated modules of display or illuminated panels. Embodiments include a system topology with an integrated modular design for multiple display or illuminated control panels, which can reduce the system weight, wiring complexity, and development expense. In embodiments, a digital chromaticity control includes in-module and cross-module control for balance and harmonization of multiple panels and modules, incorporating integrated digital signal processors and digital communications for internal and external networking.
    Type: Application
    Filed: November 24, 2010
    Publication date: September 6, 2012
    Applicant: Eaton Corporation
    Inventors: Jie Jay Chang, Vanacan Tatavoosian
  • Patent number: 8244366
    Abstract: There is provided a cochlear implant for improving the hearing ability of a patient suffered from hearing impairment comprising an internal receiving unit implanted into the body, which comprises a receiving part for receiving external signal, an active electrode and a reference electrode, characterized in that the active electrode is constructed with a single electrode wire having different thickness in at least two different regions. The active electrode of the internal receiving unit is inserted into a space formed at between the mastoid bone and the ear canal skin and end of the active electrode is inserted into the scala tympani of the cochlea and directly stimulates spiral ganglion. The cochlear implant provides easier implantation into the body and improved hearing ability at a lower cost.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 14, 2012
    Assignee: Material Solutions Technology Co., Ltd.
    Inventors: Y. Jay Chang, Dong Hyuk Lee
  • Patent number: 8155801
    Abstract: A hybrid electronics cockpit control panel system architecture is provided that includes optimized interfacing and partitioning. The architecture includes a digital function block with a digital signal processor and digital communication capabilities. The architecture also includes integrated cockpit control panels that employ a printed circuit board to avoid wire/cable connections for cockpit control panel components beyond the face panel. The architecture provides digital control and communication along a central communication bus that can eliminate the need for dedicated wire connections between the control panel and the electrical components throughout the aircraft, reducing weight and volume. One example aircraft cockpit control panel system includes a control signal processor that receives electrical control signals from pilot operating devices on the control panel and transforms them into digital status signals for communication on a communication bus.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: April 10, 2012
    Assignee: Eaton Corporation
    Inventors: Jie Jay Chang, Van Tatavoosian
  • Patent number: 7898028
    Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: March 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Jay Chang, Shien-Yang Wu
  • Patent number: 7897501
    Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: March 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Li Cheng, Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shen Chen
  • Publication number: 20100235015
    Abstract: A hardware-based control and communication architecture communicates a plurality of signals within a vehicle. The communication architecture has a transmitting portion including a signal receiving portion configured to obtain or receive a first plurality of signals, a signal consolidation circuit, a signal driver capable of transmitting a consolidated signal representative of the first plurality of signals from the signal consolidation circuit, and a clock signal generator configured to provide a synchronizing timing signal having an established or fixed period. The signal consolidation circuit may include hardware logic to provide successive data transmission windows based on the established or fixed period of the timing signal, and the consolidation circuit may be configured to transmit each of the first plurality of signals in successive data transmission windows. Bidirectional and redundant system configurations are also disclosed with a plurality of transmission mediums.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Applicant: Eaton Corporation
    Inventor: Jie Jay Chang
  • Publication number: 20100204854
    Abstract: A hybrid electronics cockpit control panel system architecture is provided that includes optimized interfacing and partitioning. The architecture includes a digital function block with a digital signal processor and digital communication capabilities. The architecture also includes integrated cockpit control panels that employ a printed circuit board to avoid wire/cable connections for cockpit control panel components beyond the face panel. The architecture provides digital control and communication along a central communication bus that can eliminate the need for dedicated wire connections between the control panel and the electrical components throughout the aircraft, reducing weight and volume. One example aircraft cockpit control panel system includes a control signal processor that receives electrical control signals from pilot operating devices on the control panel and transforms them into digital status signals for communication on a communication bus.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: EATON CORPORATION
    Inventors: Jie Jay CHANG, Van TATAVOOSIAN
  • Publication number: 20090005836
    Abstract: There is provided a cochlear implant for improving the hearing ability of a patient suffered from hearing impairment comprising an internal receiving unit implanted into the body, which comprises a receiving part for receiving external signal, an active electrode and a reference electrode, characterized in that the active electrode is constructed with a single electrode wire having different thickness in at least two different regions. The active electrode of the internal receiving unit is inserted into a space formed at between the mastoid bone and the ear canal skin and end of the active electrode is inserted into the scala tympani of the cochlea and directly stimulates spiral ganglion. The cochlear implant provides easier implantation into the body and improved hearing ability at a lower cost.
    Type: Application
    Filed: June 25, 2007
    Publication date: January 1, 2009
    Applicant: MATERIAL SOLUTIONS TECHNOLOGY CO., LTD
    Inventors: Y. Jay Chang, Dong Hyuk Lee
  • Publication number: 20080268602
    Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.
    Type: Application
    Filed: January 14, 2008
    Publication date: October 30, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Li Cheng, Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shun Chen
  • Publication number: 20080039488
    Abstract: 7-(3-Aminomethyl-4-methoxyiminopyrrolidin-1-yl)-1-cyclopropyl-6-fluoro-4-oxo-1,4-dihydro-1,8-naphthyridine-3-carboxylic acid methanesulfonate and hydrates thereof, processes for their preparation, pharmaceutical compositions comprising them, and their use in antibacterial therapy.
    Type: Application
    Filed: December 7, 2006
    Publication date: February 14, 2008
    Inventors: Ae Kim, Jin Lee, Ki Park, Jong Choi, Tae Lee, Jay Chang, Do Nam, Hoon Choi
  • Publication number: 20070290277
    Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.
    Type: Application
    Filed: August 23, 2007
    Publication date: December 20, 2007
    Inventors: Sun-Jay Chang, Shien-Yang Wu
  • Publication number: 20070247427
    Abstract: A versatile laser pointer and mouse combination integrates together the functions of laser pointer and mouse, also preferably includes a presentation program operation function, multimedia player program operation function, and timer to provide users with versatile functions and operation convenience during computer aided presentations, such as lectures, speeches, and the like. Furthermore, the housing and key sets of the versatile laser pointer and mouse combination may be configured to maintain the ergonomics in terms of hand touch of a mouse to be maintained without affecting the convenience of operating all the other added functions.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 25, 2007
    Inventors: Chaochi Huang, Jay Chang
  • Patent number: 7279430
    Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Jay Chang, Shien-Yang Wu
  • Patent number: 7220630
    Abstract: A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: May 22, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kaun-Lun Cheng, Shui-Ming Cheng, Yu-Yuan Yao, Ka-Hing Fung, Sun-Jay Chang
  • Patent number: 7190033
    Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: March 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Jay Chang, Chien-Li Cheng
  • Publication number: 20060283029
    Abstract: A laser level generates a first, a second and a third laser beam which are perpendicular to each other. The laser level includes a first laser generator for generating the first laser beam, a second laser generator for generating an incident laser beam, and a prism disposed in front of the second laser generator for splitting the incident laser beam into the second and the third laser beams. A plurality of vials are provided for indicating the level of the respective first, second and third laser beams, and a housing accommodates the first laser generator, the second laser generator, the prism and the vials.
    Type: Application
    Filed: November 28, 2005
    Publication date: December 21, 2006
    Inventors: Der-Shyang Jan, Jay Chang
  • Patent number: D548197
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: August 7, 2007
    Assignee: Quarton Inc.
    Inventors: Joe Yen, Jay Chang
  • Patent number: D565217
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: March 25, 2008
    Assignee: Quarton Inc.
    Inventors: Joe Yen, Jay Chang, Po-Sung Chuang