Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Abstract: An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Abstract: Data stored in nonvolatile memory on a Radio Frequency Identification (RFID) tag integrated circuit may have a “margin” associated with how strongly the data is written to the memory. Upon receiving a wireless margin read command, the RFID IC determines whether the margin for one of more data values stored in memory exceeds a margin threshold. The IC may determine the margin by applying bias voltages or currents to the memory cells storing the data values. If the determined margin does not exceed the margin threshold, the IC may respond with an error code.

Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.

Abstract: An RFID tag tuning circuit may be capable of adjusting the impedance matching between an RFID integrated circuit (IC) and an antenna on an RFID tag to increase the amount of power that the IC can extract from an incident RF wave. The tuning circuit switches a variable impedance coupling the antenna and the IC between several different impedance settings, where each impedance setting differs from an adjacent impedance setting by a respective impedance step size and at least one impedance step size has a different value than another impedance step size. The tuning circuit may switch the variable impedance by incrementing through a counter, decrementing through the counter, or performing some search algorithm. The tuning circuit may also initialize the variable impedance based on a default impedance setting or a random impedance setting derived from a random counter.

Abstract: A Radio Frequency Identification (RFID) tag integrated circuit (IC) includes a power rectifier component. The rectifier component includes a first current path formed by a first rectifying element, a second rectifying element, and a pump node coupled to the first and second rectifying elements. The first and second rectifying elements are coupled to a first phase of a radio frequency (RF) waveform while the pump node is coupled to a second phase of the RF waveform. The rectifier component also includes at least one biasing element coupled to the pump node and configured such that its terminal voltages vary with phases and amplitudes similar to that of the second phase of the RF waveform.

Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.

Abstract: A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.

Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.

Abstract: An analog processing block is arranged to receive an input signal through an AC coupling circuit. A digitally programmable voltage reference (DPVR) circuit is arranged to provide selection of a voltage reference that is DC coupled through a high impedance circuit to the AC coupling circuit. The input to the analog processing block includes the AC coupled input signal and the DC level from the selected voltage reference such that the DC level is effectively shifted for the analog processing block. The analog processing block may include any number of analog functions including: buffering, level shifting, scaling, integrating, and analog-to-digital conversion for digital signal processing, to name a few. A digital control logic circuit and a trim map can be arranged to control adjustments to the DPVR such that the effects of any non-ideal conditions on the analog processing block are minimized. The trim map may include non-volatile memory devices.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: An RFID tag tuning circuit may be capable of adjusting the impedance matching between an RFID integrated circuit (IC) and an antenna on an RFID tag to increase the amount of power that the IC can extract from an incident RF wave. The tuning circuit switches a variable impedance coupling the antenna and the IC between several different impedance settings, where each impedance setting differs from an adjacent impedance setting by a respective impedance step size and at least one impedance step size has a different value than another impedance step size. The tuning circuit may switch the variable impedance by incrementing through a counter, decrementing through the counter, or performing some search algorithm. The tuning circuit may also initialize the variable impedance based on a default impedance setting or a random impedance setting derived from a random counter.