Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.

Abstract: An example includes a capacitor case sealed to retain electrolyte, at least one anode disposed in the capacitor case, the at least one anode comprising a sintered portion disposed on a substrate, an anode conductor coupled to the substrate in electrical communication with the sintered portion, the anode conductor sealingly extending through the capacitor case to an anode terminal disposed on the exterior of the capacitor case with the anode terminal in electrical communication with the sintered portion, a cathode disposed in the capacitor case, a separator disposed between the cathode and the anode and a cathode terminal disposed on an exterior of the capacitor case and in electrical communication with the cathode, with the anode terminal and the cathode terminal electrically isolated from one another.

Abstract: An RFID tag tuning circuit may be capable of adjusting the impedance matching between an RFID integrated circuit (IC) and an antenna on an RFID tag to increase the amount of power that the IC can extract from an incident RF wave. The tuning circuit switches a variable impedance coupling the antenna and the IC between several different impedance settings, where each impedance setting differs from an adjacent impedance setting by a respective impedance step size and at least one impedance step size has a different value than another impedance step size. The tuning circuit may switch the variable impedance by incrementing through a counter, decrementing through the counter, or performing some search algorithm. The tuning circuit may also initialize the variable impedance based on a default impedance setting or a random impedance setting derived from a random counter.

Abstract: A Radio Frequency Identification (RFID) tag integrated circuit (IC) includes a power rectifier component. The rectifier component includes a first current path formed by a first rectifying element, a second rectifying element, and a pump node coupled to the first and second rectifying elements. The first and second rectifying elements are coupled to a first phase of a radio frequency (RF) waveform while the pump node is coupled to a second phase of the RF waveform. The rectifier component also includes at least one biasing element coupled to the pump node and configured such that its terminal voltages vary with phases and amplitudes similar to that of the second phase of the RF waveform.

Abstract: This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.

Abstract: One example includes a plurality of substantially planar electrodes disposed in a stack, in alignment, the stack being at least partially disk-shaped with a first major face opposing a second major face, with an edge extending between the first major face and the second major face, a pocket, with a covered portion of the stack disposed in the pocket, the pocket shaped to conform to the stack with a first portion of the pocket covering a first segment of the first major face, a second portion covering a second segment of the second major face opposite the first segment, and an edge portion covering the edge of the stack, wherein a remaining portion of the stack extends out of the pocket and a film disposed over the remaining portion of the stack, substantially covering the remaining portion.

Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.

Abstract: This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.

Abstract: This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.

Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier is constructed from a pair of hybrid RF rectifier elements that include a MOS transistor. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating regions, while an additional RF control signal is being applied to the gates of the transistors.

Abstract: One example includes a plurality of substantially planar electrodes disposed in a stack, in alignment, the stack being at least partially disk-shaped with a first major face opposing a second major face, with an edge extending between the first major face and the second major face, a pocket, with a covered portion of the stack disposed in the pocket, the pocket shaped to conform to the stack with a first portion of the pocket covering a first segment of the first major face, a second portion covering a second segment of the second major face opposite the first segment, and an edge portion covering the edge of the stack, wherein a remaining portion of the stack extends out of the pocket and a film disposed over the remaining portion of the stack, substantially covering the remaining portion.

Abstract: The present disclosure provides examples of a voltage regulator for a Radio Frequency Identification tag circuit. The voltage regulator includes a pair of native transistors. A first native transistor is coupled to a reference voltage and biased to saturation. A resistive element coupled between the gate and the drain of the transistor ensures a sufficient voltage difference between the source and the drain of the first native transistor. The second native transistor, with a gate coupled to the gate of the first native transistor, outputs a regulated voltage.

Abstract: This document discusses capacitive elements including a first, second and third electrode arranged in a stack. The third electrode is positioned between the first and second electrode. An interconnect includes a unitary substrate shared with the first and second electrodes. The interconnect is adapted to deform to accommodate the stacked nature of the first and second electrodes. The unitary substrate includes a sintered material disposed thereon.

Abstract: An example includes a capacitor case sealed to retain electrolyte, at least one anode disposed in the capacitor case, the at least one anode comprising a sintered portion disposed on a substrate, an anode conductor coupled to the substrate in electrical communication with the sintered portion, the anode conductor sealingly extending through the capacitor case to an anode terminal disposed on the exterior of the capacitor case with the anode terminal in electrical communication with the sintered portion, a cathode disposed in the capacitor case, a separator disposed between the cathode and the anode and a cathode terminal disposed on an exterior of the capacitor case and in electrical communication with the cathode, with the anode terminal and the cathode terminal electrically isolated from one another.

Abstract: The present disclosure provides for a voltage reference circuit for Radio Frequency Identification (RFID) tag circuit. Such a circuit is formed in a substrate that is lightly doped with impurities of a first polarity. A first transistor having a first source connected to a ground, a first gate doped with impurities of the first polarity, and a first drain connected to the first gate at a reference node, a reference current source to provide a reference current to the reference node for generating a first reference voltage at the reference node, and an additional component for receiving the first reference voltage are disclosed.

Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.

Abstract: A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.