Patents by Inventor Jay Yoder
Jay Yoder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170004965Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. BURGHOUT, Dennis Lee CONNER, Michael J. SEDDON, Jay A. YODER, Gordon M. GRIVNA
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Patent number: 9484210Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.Type: GrantFiled: April 20, 2015Date of Patent: November 1, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20160079095Abstract: A method of forming a semiconductor device package. Implementations may include providing an adhesive tape; contacting at least one electrical contact of at least one die with an adhesive surface of the adhesive tape; mechanically and electrically coupling at least one clip with the at least one die and contacting an electrical contact of the at least one clip with the adhesive surface; one of overmolding and encapsulating the at least one die and a majority of the at least one clip with one of a mold compound and an encapsulating compound, respectively, wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are not one of overmolded and encapsulated, forming the semiconductor device package; removing the semiconductor device package from the adhesive surface; and including no leadframe in the package.Type: ApplicationFiled: September 11, 2014Publication date: March 17, 2016Inventors: Stephen St. Germain, Roger M. Arbuthnot, Jay A. Yoder, Dennis Lee Conner
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Publication number: 20150228494Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 9034733Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: GrantFiled: January 21, 2014Date of Patent: May 19, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20140134828Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 8664089Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Publication number: 20140051232Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: ApplicationFiled: August 20, 2012Publication date: February 20, 2014Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Patent number: 8574961Abstract: A semiconductor device (10) is made by mounting the bottom surfaces (31, 44, 54) of a semiconductor die (14) and a lead (15, 17) on a tape (12) and over a hole (19) in the tape. A vacuum is drawn through the hole to secure the die in place when the lead's top surface (43) is wirebonded to a top surface (32) of the semiconductor die. A molding material (49) is formed to encapsulate the top surface of the semiconductor die and to expose its bottom surface.Type: GrantFiled: April 29, 2003Date of Patent: November 5, 2013Assignee: Semiconductor Components Industries, LLCInventors: James Howard Knapp, Jay A. Yoder, Harold G. Anderson
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Patent number: 8319323Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: GrantFiled: December 20, 2004Date of Patent: November 27, 2012Assignee: Semiconductor Components Industries, LLCInventors: James P. Letterman, Jr., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Patent number: 8253239Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: GrantFiled: November 30, 2010Date of Patent: August 28, 2012Assignee: Semiconductor Components Industries, LLCInventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Publication number: 20110068451Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7875964Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: GrantFiled: February 7, 2007Date of Patent: January 25, 2011Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7820528Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: August 4, 2009Date of Patent: October 26, 2010Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Publication number: 20100000772Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: ApplicationFiled: December 20, 2004Publication date: January 7, 2010Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.Inventors: James P. Letterman, JR., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Publication number: 20090298232Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: ApplicationFiled: August 4, 2009Publication date: December 3, 2009Inventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7598123Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.Type: GrantFiled: March 2, 2007Date of Patent: October 6, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman
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Patent number: 7588999Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: October 28, 2005Date of Patent: September 15, 2009Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7508060Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.Type: GrantFiled: September 24, 2007Date of Patent: March 24, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7498195Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.Type: GrantFiled: February 12, 2007Date of Patent: March 3, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder