Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

Abstract: A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

Abstract: Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.