Abstract: A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity.

Abstract: Electrical shorts caused by diffusion of residual fluorine in metallic layers can be retarded or eliminated by forming fluorine-blocking structures. A stack of alternating layers including electrically insulating layers and electrically conductive layers with a vertically extending trench is provided. In one embodiment, an insulating spacer can be formed by depositing a silicon nitride layer and partially or fully converting the silicon nitride layer into a silicon oxynitride layer, and by performing an anisotropic etch. Alternatively, an insulating spacer can be formed by forming a stack of a silicon nitride layer and a silicon oxide layer, and by performing an anisotropic etch. The silicon nitride layer or the silicon oxynitride layer can retard fluorine diffusion. Yet alternately, sidewalls of the electrically conductive layers can be nitrided to form metallic nitride portions that retard fluorine diffusion.

Abstract: Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel.

Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

Abstract: A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.

Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.

Abstract: A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.

Abstract: Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel.

Abstract: A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.

Abstract: A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.

Abstract: A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.

Abstract: A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.

Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.

Abstract: Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one opening in the stack, forming at least a portion of a memory film in the at least one opening and forming a first portion of a semiconductor channel followed by forming a second portion of the semiconductor channel in the at least one opening. The second portion of the semiconductor channel comprises silicon and germanium and contains more germanium than a first portion of the semiconductor channel which is located closer to the memory film than the second portion.

Abstract: A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere.

Abstract: A monolithic three-dimensional memory structure includes a memory stack structure including a memory film and a semiconductor channel. Traps and/or defects within the semiconductor channel and/or at the semiconductor/dielectric material interface and/or inside dielectric materials can be passivated by an anneal in a deuterium-containing gas, which replaces hydrogen atoms within the semiconductor channel or passivate the dangling bonds/traps with deuterium atoms. The anneal may be performed immediately after formation of the semiconductor channel, before or after formation of a dielectric core or a drain region, after replacement of sacrificial material layers with conductive material layers, after dicing of a substrate into semiconductor chips, or at another suitable processing step.

Abstract: A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.