Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

Abstract: A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

Abstract: A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.

Abstract: A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Abstract: A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL.

Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.

Abstract: A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.

Abstract: Devices and methods for pedestrian navigation are disclosed. In an embodiment, a device includes an accelerometer sensor configured to sense acceleration components associated with a device motion in a plurality of axes of the accelerometer sensor. The acceleration components include stride frequency components and step frequency components. The device includes a processing module communicably associated with the accelerometer sensor. The processing module is configured to process at least a portion of the acceleration components to determine an estimated attitude associated with the device motion with respect to the accelerometer sensor. The processing module is configured to filter out the step frequency components by blocking the stride frequency components. The processing module is further configured to determine the estimated attitude based on the step frequency components to thereby mitigate a bias in the estimated attitude associated with a lateral sway of the device motion.

Abstract: A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase.

Abstract: A system comprises a plurality of sensors, a sensor processor, and a sampling rate engine. The sensor processor is coupled to an output of each sensor of the plurality of sensors. The sensor processor estimates user dynamics in response to a first output signal of a first sensor of the plurality of sensors. The sampling rate engine is coupled to an output of the sensor processor. The sampling rate engine determines a sampling rate value of a second sensor of the plurality of sensors in response to a user dynamics value from the sensor processor. The second sensor comprises a selectable sampling rate. The selectable sampling rate is configured in response to the sampling rate value determined by the sampling rate engine.

Abstract: A positioning server has a positioning database. The positioning database is configured to store information relating wireless local area network (WLAN) access point (AP) signal measurements to points of a geographic positioning grid. motion information provided by dead-reckoning systems of a plurality of wireless devices and reference location information provided by at least one of a satellite positioning system and a wireless local area network (WLAN) positioning system of each wireless device is also stored. WLAN access point (AP) signal measurements acquired by each wireless device in correspondence with the motion information is stored as are non-causally determine positions of the wireless devices based on the motion information and reference locations. Positioning server is also configured to generate a geographic positioning grid that relates the AP signal measurements to points of the positioning grid based on the determined positions.

Abstract: A system for crowd-sourced fingerprinting has a positioning database and a mobile wireless device. The positioning database is configured to store information relating wireless local area network access point (AP) signal measurements to points of a geographic positioning grid. The mobile wireless device has a satellite positioning system, a transceiver, a motion measurement system, and position estimation logic. The position estimation logic is configured to determine a reference location as the device passes between areas of satellite positioning signal reception and satellite positioning signal non-reception. The device further configured to record measurements of movements provided by the motion measurement system and measurements of signals provided by the transceiver within areas of non-reception and to provide results to the positioning database.

Abstract: A system comprises a plurality of sensors, a sensor processor, and a sampling rate engine. The sensor processor is coupled to an output of each sensor of the plurality of sensors. The sensor processor estimates user dynamics in response to a first output signal of a first sensor of the plurality of sensors. The sampling rate engine is coupled to an output of the sensor processor./ The sampling rate engine determines a sampling rate value of a second sensor of the plurality of sensors in response to a user dynamics value from the sensor processor. The second sensor comprises a selectable sampling rate. The selectable sampling rate is configured in response to the sampling rate value determined by the sampling rate engine.