Abstract: A personal navigation device configured to determine heading readings continuously using data from a sensor in the personal navigation device. Heading readings are selected corresponding to a periodic event. A representative heading is determined from the selected heading readings. When a portion of the selected heading readings has a value within a range of the representative heading, a static heading indicator is asserted to indicate the personal navigation device is moving in a static heading. The static heading indicator may be used to smooth an estimated trajectory of the personal navigation device.

Abstract: Undesired variations in a signal are removed by initializing two boundaries comprising an upper boundary and a lower boundary to track the signal level. At least one of the upper boundary and the lower boundary is adjusted encapsulate/track the received signal between the two boundaries when the signal level is outside of the two boundaries. A value computed with reference to at least one of the boundaries is provided as a filter output. As a result, the output comprises desired variations that cross the boundaries and the undesired variations that are within the boundaries are eliminated. In one embodiment, an altimeter sensor signal is filtered such that the undesired variations due to noise and instability of the altimeter are removed and the desired variations representing the change in the altitude are detected and provided without any delay to the navigation subsystem.

Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

Abstract: Apparatus and method for positioning a wireless device. In one embodiment, a method for indoor positioning includes determining a reference location of a wireless device, based on satellite positioning, as the device passes between areas of satellite positioning signal reception and satellite positioning signal non-reception. While in the areas of non-reception, signals transmitted by wireless local area network (WLAN) access points (APs) and parameters of motion of the device are measured. Positions of the device are estimated while in the areas of non-reception based on the reference location and the parameters of motion. A positioning grid for positioning is generated based on the signals measured by the wireless device at the estimated positions.

Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Abstract: A system (10) for pedestrian use includes an accelerometer (110) having multiple electronic sensors; an electronic circuit (100) operable to generate a signal stream representing magnitude of overall acceleration sensed by the accelerometer (110), and to electronically correlate a sliding window (520) of the signal stream with itself to produce peaks at least some of which represent walking steps, and further operable to electronically execute a periodicity check (540) to compare different step periods for similarity, and if sufficiently similar then to update (560) a portion of the circuit substantially representing a walking-step count; and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the step count. Other systems, electronic circuits and processes are disclosed.

Abstract: A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.

Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

Abstract: A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.

Abstract: A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Abstract: A personal navigation device configured to determine heading readings continuously using data from a sensor in the personal navigation device. Heading readings are selected corresponding to a periodic event. A representative heading is determined from the selected heading readings. When a portion of the selected heading readings has a value within a range of the representative heading, a static heading indicator is asserted to indicate the personal navigation device is moving in a static heading. The static heading indicator may be used to smooth an estimated trajectory of the personal navigation device.

Abstract: A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison.