Patents by Inventor Jaydeb Goswami
Jaydeb Goswami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074160Abstract: A variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. The memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. The integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. The step height reduction in the memory device can lower overlap capacitance.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Shivani Srivastava, Russell Allen Benson, Raghunath Singanamalla, Jaydeb Goswami
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Patent number: 11825662Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.Type: GrantFiled: July 16, 2021Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Clement Jacob, Vassil N. Antonov, Jaydeb Goswami, Albert Liao, Christopher W. Petz, Durai Vishak Nirmal Ramaswamy
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Publication number: 20210343732Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Applicant: Micron Technology, Inc.Inventors: Clement Jacob, Vassil N. Antonov, Jaydeb Goswami, Albert Liao, Christopher W. Petz, Durai Vishak Nirmal Ramaswamy
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Patent number: 11101274Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir. Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.Type: GrantFiled: December 5, 2019Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Clement Jacob, Vassil N. Antonov, Jaydeb Goswami, Albert Liao, Christopher W. Petz, Durai Vishak Nirmal Ramaswamy
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Publication number: 20210175239Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.Type: ApplicationFiled: December 5, 2019Publication date: June 10, 2021Applicant: Micron Technology, Inc.Inventors: Clement Jacob, Vassil N. Antonov, Jaydeb Goswami, Albert Liao, Christopher W. Petz, Durai Vishak Nirmal Ramaswamy
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Patent number: 11011378Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.Type: GrantFiled: July 1, 2019Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Yiping Wang, Caizhi Xu, Pengyuan Zheng, Ying Rui, Russell A. Benson, Yongjun J. Hu, Jaydeb Goswami
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Publication number: 20210005455Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventors: Yiping Wang, Caizhi Xu, Pengyuan Zheng, Ying Rui, Russell A. Benson, Yongjun J. Hu, Jaydeb Goswami
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Patent number: 10147727Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: GrantFiled: February 13, 2018Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Publication number: 20180175039Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Applicant: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Publication number: 20180138182Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: ApplicationFiled: November 11, 2016Publication date: May 17, 2018Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Patent number: 9972628Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: GrantFiled: November 11, 2016Date of Patent: May 15, 2018Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Patent number: 9397105Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.Type: GrantFiled: September 9, 2013Date of Patent: July 19, 2016Assignee: Micron Technology, Inc.Inventor: Jaydeb Goswami
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Publication number: 20160118340Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.Type: ApplicationFiled: November 13, 2015Publication date: April 28, 2016Inventors: Jaydeb Goswami, Allen McTeer
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Patent number: 9202786Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.Type: GrantFiled: December 29, 2010Date of Patent: December 1, 2015Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Allen McTeer
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Publication number: 20150303147Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.Type: ApplicationFiled: June 26, 2015Publication date: October 22, 2015Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
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Patent number: 9142670Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.Type: GrantFiled: May 12, 2014Date of Patent: September 22, 2015Assignee: Micron Technology, Inc.Inventor: Jaydeb Goswami
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Patent number: 9099472Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.Type: GrantFiled: October 25, 2013Date of Patent: August 4, 2015Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
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Patent number: 8846512Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.Type: GrantFiled: July 8, 2013Date of Patent: September 30, 2014Assignee: Micron Technology, Inc.Inventor: Jaydeb Goswami
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Publication number: 20140248760Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: Micron Technology, Inc.Inventor: Jaydeb Goswami
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Patent number: 8748273Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.Type: GrantFiled: June 15, 2012Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventor: Jaydeb Goswami