Patents by Inventor Jaynal Molla

Jaynal Molla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167033
    Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.
    Type: Application
    Filed: January 18, 2021
    Publication date: June 3, 2021
    Inventors: Tianwei Sun, Jaynal A. Molla
  • Patent number: 10923451
    Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Tianwei Sun, Jaynal A. Molla
  • Publication number: 20210020595
    Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Tianwei Sun, Jaynal A. Molla
  • Patent number: 10861764
    Abstract: Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Mahesh K. Shah, Lu Li, David Abdo, Geoffrey Tucker, Carl Emil D'Acosta, Jaynal A. Molla, Justin Eugene Poarch, Paul Hart
  • Patent number: 10825747
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: November 3, 2020
    Assignee: NXP USA, INC.
    Inventors: Li Li, Jaynal A. Molla, Lakshminarayan Viswanathan
  • Publication number: 20200335398
    Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.
    Type: Application
    Filed: July 3, 2020
    Publication date: October 22, 2020
    Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
  • Publication number: 20200335420
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 10741446
    Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 11, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jaynal A Molla, Lakshminarayan Viswanathan, David Abdo, Colby Greg Rampley, Fernando A. Santos
  • Patent number: 10727153
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A Molla
  • Patent number: 10529638
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10485091
    Abstract: High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, Elie A. Maalouf, Geoffrey Tucker
  • Patent number: 10431449
    Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jaynal A. Molla, Lakshminarayan Viswanathan, Geoffrey Tucker
  • Patent number: 10396006
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: August 27, 2019
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Publication number: 20190206759
    Abstract: Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventors: Lakshminarayan Viswanathan, Mahesh K. Shah, Lu Li, David Abdo, Geoffrey Tucker, Carl Emil D'Acosta, Jaynal A. Molla, Justin Eugene Poarch, Paul Hart
  • Publication number: 20190148138
    Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 16, 2019
    Applicant: NXP USA, INC.
    Inventors: JAYNAL A. MOLLA, LAKSHMINARAYAN VISWANATHAN, GEOFFREY TUCKER
  • Patent number: 10269678
    Abstract: Microelectronic systems having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the step or process of obtaining a microelectronic component from which a heat dissipation post projects. The microelectronic component is placed or seated on a substrate, such as a multilayer printed circuit board, having a socket cavity therein. The heat dissipation post is received in the socket cavity as the microelectronic component is seated on the substrate. Concurrent with or after seating the microelectronic component, the microelectronic component and the heat dissipation post are bonded to the substrate. In certain embodiments, the heat dissipation post may be dimensioned or sized such that, when the microelectronic component is seated on the substrate, the heat dissipation post occupies a volumetric majority of the socket cavity.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Mahesh K. Shah, Lu Li, David Abdo, Geoffrey Tucker, Carl Emil D'Acosta, Jaynal A. Molla, Justin Eugene Poarch, Paul Hart
  • Publication number: 20190109060
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190098743
    Abstract: High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Applicant: NXP USA, INC.
    Inventors: JAYNAL A. MOLLA, LAKSHMINARAYAN VISWANATHAN, ELIE A. MAALOUF, GEOFFREY TUCKER
  • Publication number: 20190051571
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA
  • Publication number: 20190043775
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Applicant: NXP USA, INC.
    Inventors: AUDEL SANCHEZ, LAKSHMINARAYAN VISWANATHAN, FERNANDO A. SANTOS, JAYNAL A. MOLLA