Abstract: The present invention relates to a liquid crystal display and a driving method thereof. The liquid crystal display of the present invention includes a pixel electrode including: a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other; a first thin film transistor connected to the first subpixel electrode; a second thin film transistor connected to the second subpixel electrode; a third thin film transistor connected to the third subpixel electrode; a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode; a first gate line connected to the first to third thin film transistors; a second gate line connected to the fourth thin film transistor; a data line connected to the first and second thin film transistors; and a storage electrode line connected to the third thin film transistor.

Abstract: Embodiments of the present invention relate to a liquid crystal display and a driving method thereof. According to an embodiment, the liquid crystal display comprises a pixel electrode having a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other. The liquid crystal display comprises a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, and a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode. The liquid crystal display comprises a first gate line connected to the first to third thin film transistors, a second gate line connected to the fourth thin film transistor, a data line connected to the first and second thin film transistors, and a storage electrode line connected to the third thin film transistor.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A display device includes a display area and a non-display area, a first alignment layer disposed on a first substrate, a second alignment layer disposed on a second substrate, a liquid crystal layer disposed between the first alignment layer and the second alignment layer; and a groove disposed in the non-display area of the second substrate to correspond to at least a portion of an end portion of the second alignment layer. The groove is provided along at least one side of the display area and is configured to be filled by an alignment solution used to from the second alignment layer and prevent the alignment solution from dispersing to other areas of the second substrate.

Abstract: A display device including a base substrate, a pixel disposed on the base substrate, and a color filter part disposed between the base substrate and the pixel. The color filter part includes a color filter corresponding to the pixel and a black matrix disposed at at least a side of the color filter. The pixel includes a cover layer defining a tunnel-shaped cavity on the base substrate, an image display part disposed in the tunnel-shaped cavity, and first and second pixel electrodes and a common electrode applying an electric field to the image display part. The tunnel-shaped cavity is formed by forming a sacrificial layer and wet-etching the sacrificial layer.

Abstract: Provided are a display device and a manufacturing method thereof capable of preventing aggregation of an alignment layer and maintaining uniformly a cell-gap. The display device according to an exemplary embodiment of the invention includes: a substrate including a plurality of pixel areas; a thin film transistor formed on the substrate; a pixel electrode connected to the thin film transistor and formed in the pixel area; a barrier layer formed on the pixel electrode; a roof layer formed on the barrier layer to be spaced apart from the barrier layer with a microcavity therebetween; and a liquid crystal formed to fill the microcavity.

Abstract: A liquid crystal display includes an insulation substrate, a pixel electrode, a microcavity layer, a common electrode, and a layer. The pixel electrode is disposed on the substrate. The microcavity layer is disposed on the pixel electrode and includes a plurality of microcavities including liquid crystal molecules disposed therein. The common electrode is disposed on the microcavity layer. The layer is disposed on the common electrode and includes an organic material. The layer comprises a refractive index of more than 1.6 and less than 2.0.

Abstract: A display panel includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first and second substrates. The first substrate includes a recess portion recessed into the first substrate from the surface of a common electrode and a first alignment barrier protruded from the recess portion in an area corresponding to at least a portion of an end portion of a first alignment layer.

Abstract: A liquid crystal display device may include a substrate. The liquid crystal display device may further include a pixel electrode disposed on the substrate. The liquid crystal display device may further include a common electrode overlapping the pixel electrode, wherein a liquid crystal injection hole is formed through at least the common electrode. The liquid crystal display device may further include a liquid crystal layer disposed between the pixel electrode and the common electrode. The liquid crystal display device may further include a light-blocking element disposed inside the liquid crystal injection hole.

Abstract: A display device including a base substrate, a pixel disposed on the base substrate, and a color filter part disposed between the base substrate and the pixel. The color filter part includes a color filter corresponding to the pixel and a black matrix disposed at at least a side of the color filter. The pixel includes a cover layer defining a tunnel-shaped cavity on the base substrate, an image display part disposed in the tunnel-shaped cavity, and first and second pixel electrodes and a common electrode applying an electric field to the image display part. The tunnel-shaped cavity is formed by forming a sacrificial layer and wet-etching the sacrificial layer.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.

Abstract: In a thin film transistor array panel according to an exemplary embodiment of the present invention, a plasma process using a mixed gas including hydrogen gas and nitrogen gas with a ratio of a predetermined value is undertaken before depositing a passivation layer. In this manner, performance deterioration of the thin film transistor may be prevented and simultaneously, haze in a transparent electrode may be prevented. Alternatively, a first passivation layer is depsoited, then removed. A passivation layer is again re-deposited, such that little or no haze is present in the resulting passivation layer.

Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Abstract: A display apparatus includes a first insulating substrate on which pixels are arranged and a second insulating substrate facing the first insulating substrate. Each pixel includes a gate electrode disposed on the first insulating substrate, a gate insulating layer disposed on the first insulating substrate to cover the gate electrode, a semiconductor pattern disposed on the gate insulating layer to overlap with the gate electrode, a source electrode and a drain electrode disposed on the semiconductor pattern, a transparent pixel electrode disposed on the gate insulating layer and partially making contact with the drain electrode, a protective layer disposed on the pixel electrode, and a common electrode disposed on the first insulating substrate or the second insulating substrate to form an electric field together with the pixel electrode.

Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.