Abstract: The invention discloses a method and an apparatus for use in high speed networks such as Asynchronous Transfer Mode (ATM) networks providing support for processing multipriority data flows at media speed, the major constraint being to share the storage and the ALU between all the tasks. The invention consists first in grouping the tasks in processes and the processes in set of processes all organized in decreasing order of their priority ; `on the fly`interruption of a lower priority process/set of processes by a higher priority process/set of processes is possible as well as reuse of the shared resources during task void states inactive in a process or between processes.In the preferred embodiment of the invention, the support of the reserved bandwidth and non reserved bandwidth ATM services data flows requires two different groups of processes, the highest priority being for the group of processes serving the reserved bandwidth service.

Abstract: The method and apparatus of the present invention solve the problem of scheduling the transmission of cells in packet switched networks having network connections requiring a minimum bandwidth at connection establishment. The method and the apparatus further support any mixed traffic flow including connections requiring a minimum bandwidth, a fixed reserved bandwidth or no bandwidth at connection establishment. Scheduling is controlled by a dual scheduling mechanism having a first scheduler, triggered by absolute time, for scheduling the minimum service connections up to a rate corresponding to their reserved minimum bandwidth, a second scheduler and a queue of minimum service connection identifiers for communication between the two scheduling schemes.

Abstract: The invention discloses a method and an apparatus for implementing the physical interface in a network element connected to a packet network such as Asynchronous Transfer Mode (ATM) network. With the solution of the invention, the physical interface functions can be integrated on one chip for more than one network port. The physical interface is provided between port bit streams at media speed and word data flow transferred onto/from a bus which is under the control of the network equipment. The solution of the invention includes grouping logics and storage elements by islands of more than one port. Furthermore, the logics and storage elements for statistical counting operations can be grouped for a processing generalized to all ports.

Abstract: The invention discloses a method and an apparatus for in-line and on-site updating of Field Programmable Gate Arrays with remote loaded configuration data files. Flash EEPROMs which are used because of their non-volatile memories and their high density, are storing more than one configuration data file. The memories are divided in more than one part, each part of the memory for storing one configuration data file. One part of the memory also contains a flag identifying the currently loaded configuration data file. The Flash EPROM's bits being set to one same binary value before any writing operation, including the update of the configuration data file containing the flag. The setting of the bits to said binary value always identifies a valid other configuration data file in order to insure a correct re-loading of the FPGAs in case of reception of an unexpected event leading to an initialization.

Abstract: A communication system comprises a plurality of nodes interconnected by links comprising a plurality of connections. The traffic between the nodes is set up by a reserved bandwidth service and/or a non reserved bandwidth service. The non reserved bandwidth service is controlled by a hop by hop backpressure mechanism. When the traffic entering a node exceeds a high threshold, the backpressure mechanism generates stop backpressure primitives in order to throttle the entering traffic. In case of congestion the mechanism is either able to selectively interuppt the connection contributing to the congestion without affecting the rest of the link traffic, or to globally stop all link traffic. Traffic can be resumed if traffic rates fall below the low threshold values.

Abstract: An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.

Abstract: A data switch is described with a multi-port data switching element, one or more input/output adapters for receiving user data cells from outside the switch and for transmitting cells switched through the switching element to a network outside the switch, and a control element including a control processor. To reduce the complexity of the data switch, the single control processor is used to control operations of hardware modules on both the the control element on which the processor is located and on the input/output adapters. The control is provided by means of control cells which generally traverse the same data paths as user data cells and generally conform to the format of user data cells, at least within the data switch. Both the control processor and the hardware modules are capable of generating control cells and transmitting them toward a target, either the control processor or hardware modules.

Abstract: A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46).

Abstract: A multicasting apparatus and method for an Asynchronous Transfer Mode (ATM) switch is described, which uses a single target port (TP) vector attached to each outgoing ATM cell. The target port vector contains identifiers of each port to which the cell has to be transmitted. After transmission of the cell, the identifier relating to respective target port is erased from the TP vector. Hence the TP vector contains only identifiers of target port to which the cell has not yet been transmitted. When the TP vector contains no identifiers, the storage location at which the ATM cell is stored during the transmission, is freed for another cell. Unicast and multicast traffic are treated identically.

Abstract: A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.

Abstract: The techniques required to switch an ATM cell between an input adapter and an output adapter are enhanced by performing two look-up operations. The first look-up operation is performed in the input adapter which receives the cell to be switched. The first look-up operation retrieve the address of the target output port and a connection control block. The second look-up operation is performed in the target output adapter and makes use of the results of the input adapter search to retrieve the information need to complete the transfer of the cell to the target output port.

Abstract: A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.

Abstract: Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased).

Abstract: An apparatus and method for multicasting messages stored in data buffers of a data storage. Each message is composed of data stored in a plurality of the data buffers. Each data buffer is controlled and mapped to a unique direct control block (DCB) which stores information characterizing the data buffer. By chaining the DCBs variable length, messages can be generated. Indirect control blocks (ICB) stores information characterizing the data or messages duplicated and points to a DCB. A field in the DCB carries a count representing the number of times the message is to be duplicated.

Abstract: In a packet switched communications system an incoming real-time packet is imbedded after the next block of data of the non-real-time packet being transmitted. This object is accomplished by transmitting each packet along with at least a 1-byte trailer which is used to indicate the packet type, whether the current block of non real time data is preempted or whether the current block of non real time data is resumed.

Abstract: A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.

Abstract: The arbitrating method is based on the classification of the users into different categories, and the assignment to all users in a category of an identical privilege level which characterizes the interruption capability of the users in the category. A task performed by a selected user in a category can only be interrupted for granting access to the resource to a user in a category having a higher privilege level. Also a normal preference level is assigned to each user within a category, which determines the selection order of the users in the category. The privilege level of a user category combined with the preference level of each user constitutes the priority level of the user. The access to the resource is granted to a selected user having the highest priority level.

Abstract: A system for providing a plurality of timers to perform the timing of event occurrences wherein, for each event, there corresponds a timer control block which stores in its time-flag field (Tf) an indication of whether the timer control block is chained or unchained, running or stopped, in its time-out field (Tv) the expiration time interval and in its time-stamp field (Ts) the current time as a reference at each interruption. The timer control blocks are chained by a one-way link according to their expiration times in such a way that each timer chain contains the timer control blocks whose events will occur at the same time. A cyclic table of index values classifies the timer chains according to their expiration times.

Abstract: An error correction apparatus includes an error control circuit which computes for each burst of a message (for a destination unit) an error correction code as a function of an initial error correction code at the first burst of the message or of the error correction code of the previous burst and of the data bytes of the burst. The burst error correction code is sent on a medium which is separate from the data transport medium as a companion of the burst. Also, the error control circuit receives the burst error correction code from an origin unit and generates the burst error correction code to be compared with the received burst error correction code. If a mismatch is detected, the burst found in error is flagged.

Abstract: The invention includes a bridge having n ports (n>1), each port being connected to a Token-Ring physical segment, each physical segment having one native Token-Ring workstation attached. The bridge to the workstations a single Token-Ring logical segment with a single Active Monitor and a single Ring Number. The invention includes a centralized medium access control (MAC) function inside a centralized processor instead of a MAC function implemented at each port of the bridge; the frame handling function, due to the fixed and limited configuration (same bridge Active Monitor seen by all connected stations), does not require a multi-port bridge function, but a simpler switch function between ports. Bridge clocking is also simplified, and a cost effective unshield twisted pair (UTP) retiming solution is presented.