Abstract: The connection capability of a communication controller is extended. The communication controller includes a central control unit CCU, running a network control program NCP stored in a memory having a direct memory access facility through a DMA bus. The input/output bus of the communication controller and DMA bus are connected to line adapters, and channel adapters and a controller extension through a coupler which allows additional adapters to be connected to the controller. At initialization, a table is built into a coupler memory, which is then used in steady state mode for controlling the transmission of the messages to the additional users and the reception of the messages from the additional users, by improving the buffer unchaining and chaining processes into the NCP memory.

Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

Abstract: This invention relates to a protocol implemented in a communication system for exchanging data and control messages between adapters to which are attached different users, and a shared memory subsystem comprising a depository storage, a manager of storage and a microprocessor. Such protocol enables the adapters to be the initiators of the transmission and reception of data by using the control lines that connect the manager of storage to all adapters in the same way as the data bus and the address bus. Moreover, the adapters slice the messages into data bursts to which are associated control words specifying the sizes, the owner and the position of the burst in the message. Consequently, those data bursts may be interleaved when transiting on the data bus without the intervention of the microprocessor for the routing, and they will be stored in or read from the depository storage according to the identification of the user in the control word.

Abstract: A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

Abstract: In a communication node (10) which comprises switching device (24) operating under control of a clock signal of period T for exchanging information slots carried in external frames of period T' comprising n slots, with each slot comprising a x-bit data byte, between external Time Division Multiplex TDM links (12,14) attached to the communication node, a synchronization device prevents the slippage phenomena due to the asynchronies between T and T' from causing a loss of data slots by generating at the input of the switching means internal frames from the received external frames. These internal frames are synchronous with the clock signal of period T and have a format which allows the slippage to be compensated.

Abstract: The hybrid packet and circuit switching system allows merging of packet and circuit traffic from user interface modules on a TDM bus and transfer of packet information from one module to another module or the exchange circuit information between modules. Circuit exchanges or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. A routing indication common to the packet and circuit bursts is used for controlling the switching of the bursts by the switch 1. The indication is performed by piggy backing the target module address for the circuit bursts, as well as for the packet burst, with the data bursts. Marking tables needed for the circuit burst allocation are located in the user interface modules.

Abstract: An Active Remote Module (ARM) attaches end user devices to any port of a multiport communications processing unit. The ARM includes circuit arrangements which receive serial streams of data and clock information which are arranged into data slots, control slots and outband slot carrying characteristic information, including ARM address, ARM type, end user data rate, etc., about the ARM and the end user devices. By issuing selective commands, a line adapter in the multiport communications processing unit is made aware of the user devices connected to its port and structure the data to meet the requirement of the attached end user devices.

Abstract: A device which switches data processing from an active processor, about to fail, to a back-up processor includes a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establishing recovery point signals generated by the active processor to be dumped into the memory of the back-up processor so that the back-up processor resumes operation of the active processor from the last established recovery point.

Abstract: A distribution mechanism includes a scheduling device which partitions a common timing signal with a period T into n slots of t duration each, a configuration table having n addressable locations with each of the n locations storing communication control information and addressable by slot numbers generated by the scheduling device and a distribution buffer device (2) having at least a first and a second part, with each part having n addressable locations addressed by control information provided by the configuration table during each slot period to cause an interface involved in the to be established communications during a selected slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot generated by the schedule means.

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

Abstract: The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N<n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical "1's" as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).

Abstract: Interconnection system for attaching a maximum number n of equipment users EU (DCE or DTE) to the line adapter (2) of a communication processing unit. The user data and control bits are carried on transmit and receive serial link 4 and 6 in data and control slot entities arranged in frame of period T, comprising one entity per user. These entities are allocated to the user equipments through multiplexing/demultiplexing circuit (10), link adapters (12-1) to (12-8) and connecting boxes (30-1) to (30-8). The user equipments are connected through active remote modules which are specific to the standardized interfaces of the user equipments. Link adapters (12-1) to (12-8) add to the data and control slot entities an outband slot which is used for exchanging control information, such as the active remote module address and type which are stored in memory (42), to be transmitted to the line adapter (2). The advantage of the interconnection system is that the attachment of the user equipments is simplified.

Abstract: A process for updating the frame check sequence FCS.sub.r (X) of a digital frame including an embedded variable header polynomial H.sub.r (x), said process including: partitioning H.sub.r (x); XORing the modified polynomial header H.sub.t (x) and previous polynomial header H.sub.r (x) to generate a differential polynomial D(x); computing a differential frame check polynomial sequence dFCS (x) on said D(x) only and adding dFCS (x) to the polynomial FCS.sub.r (x) to form a new FCS.sub.t (x).

Abstract: A data handling system wherein data are arranged into frames including an information data section and a frame check sequence (FCS) section, and wherein a stamp section has to be appended/deleted from said frame. The stamp appending is operated without any FCS updating being required by appending to each stamp, a so called precomputed and stored anti-stamp.

Abstract: The invention relates to a mechanism to be used in an integrated packet/circuit switched telecommunication network. It allows instantaneously on a per slot basis, the re-allocation of unused bandwidth left by a circuit user source to the background packet flow, and allows giving it back to the circuit source as it resumes its activity. The circuit user data Cd are sent through the network during slots of frames which are assigned to the circuit users on a per- call basis. Interfacing means (30, 32) are provided to generate slot qualifying bits Caq which are set to a first value when the corresponding circuit users are active and to a second value when the corresponding cirucit users are inactive. These qualifying bits are transported through the network in correspondence with the slot they qualify and sensed to cause the slots having a Caq set to the second value to be filled with packet bits.

Abstract: A pseudo synchronous mechanism is used in the nodes of a communication network for exchanging non-character coded information (NCI) and potentially character coded information on inter node links. Communication is performed in frames comprising circuit slots devoted to the transportation of character coded information. The circuit slots are assigned to circuit users on a per-call basis under control of node management apparatus. The slots are qualified by at least one qualification bit (Caq) which indicates, when set to a first value (0) that the users are momentarily active and when set to a second value (1) that the users are momentarily inactive. The node mechanism includes a store in which queues of storing positions are assigned to the circuit users attached to the node. The circuit user information to be sent on the network internode links or received from the internode links is stored in the store.

Abstract: System for dynamically allocating circuit slots in frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, the frames are delimited by flags and divided into bit slots which may be used for synchronous circuit flow or asynchronous packet flow. Each node changes the flags preceding at least one frame in which at least one slot is to be added or deleted to a value including a first number of delimiting bits and a second number of bits which are coded to indicate that slot(s) is (are) to be added or deleted and the corresponding slot number sends call control packets which are propagated through the network nodes.

Abstract: Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network. Each complex frame contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256) and concludes a succession of subframes delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Divison Multiplex Frames (125 microseconds) and n being an integer number equal to or greater than 1 which depends upon the medium link bit rate and e being a period of time lower than a medium link bit period.

Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line.

Abstract: The address generating device is provided for a communication line scanning device. The lines are connected to the scanning device through n line interface circuits, n varying in accordance with the network configuration. Each interface circuit can be connected to a various number of lines, for instance one line or k lines in a preferred embodiment, and comprises means for providing to the address generating device, a presence indicating signal indicating that it is plugged and a signal indicating the number of the lines connected thereto. A first logic circuit receives the presence indicating signals as inputs and generates on its outputs the address bits of the last present interface circuit to be scanned. A first counter able to count in binary mode up to n-1 is incremented by an increment pulse provided by a clock on each period assigned to the scanning of a line. This counter outputs the address bits of the successive interface circuits.