Patents by Inventor Jean-Claude Dispensa

Jean-Claude Dispensa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030005125
    Abstract: A control system in a communication system comprising a server farm connected by means of Internet Service Provider routers to the Internet or the like. The server farm includes at least a customer WEB server and all server farm resources enabling any user connected to the Internet to access the customer WEB server by using the server farm resources. The server farm includes at least one Service Level Agreement (SLA) server for periodically monitoring the availability of a path to be used by the user to access the customer WEB server.
    Type: Application
    Filed: May 28, 2002
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Jean-Marc Berthaud, Jean-Claude Dispensa, Eric Lebrun, Jean-Bernard Schmitt
  • Patent number: 6401171
    Abstract: Method and device for caching the IP header of a message being routed through a data transmission network wherein each node includes a route processor for computing a routing algorithm, a main memory for storing the message, a cache memory; and an IP header detection logic circuit for storing the header in the cache memory as the message is being stored in the main memory. Once the header has been stored in the cache memory, it can be read from the cache memory in order to compute the routing algorithm. The new header resulting from the routing computation is written into the cache memory and is then read from the cache memory when the message including the header and the message data is sent over the network.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: June 4, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Philippe Klein, Jean-Claude Dispensa, Alexandre Jay, Jean-Philippe Loison
  • Patent number: 6182120
    Abstract: Queue processing mechanism in which queued messages are processed based on combination of queue delay and queue priority. A scheduler dequeues the highest priority non-empty Microcode Input Queue (MIQ) to serve the queued messages. If there is no critical queue, meaning that the maximum aging of one or more queues has not been reached, the critical state is not entered. A static weight for each queue is then tested to determine if there is still a message to be processed from the corresponding MIQ. Messages are dequeued from the same MIQ until the static weight is reached. The next MIQ is then served etc., until the queue of the lowest priority level is served. If the critical phase is entered, the status of the normal state is stored for later return and the MIQs in critical state are dequeued according to their critical weights. If other MIQs appear to be critical, they are served in the order of their critical priorities (or weights).
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Cesca Beaulieu, Jean-Claude Dispensa