Abstract: A method for multiple memory aliasing for a configurable system-on-a-chip, including executing code from an internal memory, locating a configuration program in the internal memory, disabling the internal memory alias, and jumping to a secondary initialization routine, is disclosed.

Abstract: A method for ensuring data coherency in buffered direct memory access (DMA) data transfers. The DMA controller realizes the last piece of data is being transferred to the write buffer. The DMA controller then sends a “Last Write Data” signal to the external memory access arbitration unit. The external memory access arbitration unit then allows completion of all pending memory operations. If a memory request occurs, a wait line is asserted such that memory operations (i.e., reading from, or writing to, the memory) are prevented for all sources other than the DMA channel associated with the “Last Write Data” signal. The external memory access arbitration unit also grants priority to the DMA channel associated with the “Last Write Data” signal. This effectively flushes the write buffer and completes the buffered DMA data transfer. The external memory access arbitration unit then deasserts any asserted wait lines and memory operations are no longer prevented.

Abstract: A method to provide hierarchical reset capabilities for a configurable system on a chip is disclosed. The method includes determining a plurality of reset functions, and establishing a reset hierarchy among the plurality of reset functions.

Abstract: The present invention provides a method for breakpoint stepping a multi-bus device. The multi-bus device includes a breakpoint unit capable of detecting bus events on multiple busses. The breakpoint unit is originally programmed to break on the detection of a specified bus event on a bus selected from multiple busses. After the specified bus event has been detected and the device has entered one of several possible frozen states, the breakpoint unit may be programmed to detect a new bus event on a bus selected from multiple busses. The method is repeated as needed to achieve breakpoint stepping, including single stepping.

Abstract: The present invention provides a hardware breakpoint unit for a multibus, processor-based, configurable circuit. The multi-bus breakpoint unit connects to and allows tracing of multiple busses and includes the ability to break on the occurrence of a pre-determined bus event on any one of the multiple busses. The multi-bus breakpoint unit can be connected to and programmed by a host debugging system via a port on the target chip.

Abstract: An integrated circuit including a processor, a processor bus coupled to the processor, a system bus and a trace buffer. The trace buffer may capture activity on either the processor bus or the system bus.

Abstract: A integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus.

Abstract: A method of communicating with a configurable system-on-chip via a test interface is described. First, an interface is coupled to a configurable system-on-chip and a first command is sent to the interface from a tester. The next command execution is then blocked. Next, the first command is executed in the configurable system-on-chip. Data is then output from the configurable system-on-chip and written to a register in the interface. The data output includes a ready bit. Next, the data from the register is read. The first bit read is an asserted ready bit. The next command execution is then enabled. When the asserted ready bit is received in the tester, the tester sends a second command to the interface. The second command is then executed in the configurable system-on-a-chip.

Abstract: A programmable input/output memory architecture. The programmable input/output memory cells are disposed in two segments about the periphery of the chip. Each segment has two data buses for separate reading and writing of the configuration register. Each cell is selected and configured according to user specifications. Corresponding memory cells from each segment share the same select line, therefore two bytes of configuration data are accessed together and the data is propagated through both segments approximately concurrently thereby reducing propagation delay.

Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.